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| 型號： | OR3LP26B |
| 英文描述： | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）嵌入式主/目標(biāo)PCI接口 |
| 文件頁數(shù)： | 95/184頁 |
| 文件大小： | 5590K |
| 代理商： | OR3LP26B |
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Lucent Technologies Inc.
Lucent Technologies Inc.
95
Data Sheet
March 2000
ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description
Quad Port
Bursting
The PCI core uses the burst count supplied during
operation setup to determine the Master read opera-
tion’s burst length (unlike the Master write, which uses
signal
mwlastcycn
). The burst length of 18 bits allows
bursts of up to 2
18
– 1 quad words to be specified. To
initiate a burst, the starting address must be aligned to
a 64-byte boundary. If
ad[2]
is a 1, a single transfer will
be executed.
Master Read Byte Enables
During master reads, byte enables are always supplied
by the Master to the Target, even though on reads the
data is flowing in the opposite direction. Thus, the byte
enables cannot be buffered in a FIFO alongside the
corresponding data. Also, the byte enables must be
presented on the bus by the Master at the same time
that the data is being presented on the bus by the Tar-
get (unless the Target uses
trdyn
to insert wait-states),
and so the data provided by the Target cannot depend
on the byte enables (once again, without wait-states).
Termination
Once initiated, Master read operations will repeat on
the PCI bus until the following occurs:
1. All data is received.
2. An abort occurs (either Master or Target).
3. The
fpga_mstopburstn
signal is asserted.
4. The PCI bus’ reset signal (
resetn
) is asserted.
If a PCI transaction is terminated with a retry or discon-
nect before all data has been received, the PCI core
will initiate another Master read operation, continuing
from that point.
Reset
The FPGA application can apply the PCI core’s reset
signal
mfifoclrn
to place the core’s master logic in a
known state. Normally, the clear signal will not be used
unless a severe problem has occurred in the data flow.
The
mfifoclrn
signal is synchronous with
fclk
and must
be asserted for a minimum of three clock periods. Dur-
ing reset, the
m_ready
signal will go low. After the
reset signal is deasserted high,
m_ready
will continue
to be low for 8—10 clock periods. The FPGA applica-
tion should not continue normal operation until
m_ready
is asserted high.
Understanding and Using the pci_mcfg_stat Status
Signals
On the Master interface, there are two signals that con-
trol and provide status to the FPGA application.
pci_mcfg_stat
provides the status, and
mcfgshiftenn
controls what information the status line provides. The
pci_mcfg_stat
signal is always active and duplicates
the status contained in configuration status register at
location offset 0x04, bits 24, 28, and 29. To use this
status output, the FPGA application must keep
mcfg-
shiftenn
= 1. When high,
pci_mcfg_stat
provides the
wired-OR of the three status lines. If
pci_mcfg_stat
gets set to a 1, indicating an error, then the FPGA
application may set
mcfgshiftenn
= 0 to determine
individual status. Once low, the
pci_mcfg_stat
signal
will output data parity error detected on the first clock,
target abort received on the second clock, and master
abort received on the third clock.
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| OR3LP26BBA352-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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| OR3T125 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-4BC432I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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