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參數(shù)資料
| 型號： | OR3LP26B |
| 英文描述： | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）嵌入式主/目標PCI接口 |
| 文件頁數(shù)： | 110/184頁 |
| 文件大?。?/td> | 5590K |
| 代理商： | OR3LP26B |
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110
LLucent Technologies Inc.
ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description
Quad Port
(continued)
Target (PCI Bus Initiated) Read
The Target read operation presents unique demands
on the PCI core because only in the Target read opera-
tion does the PCI core request data that is needed to
complete the transaction after the PCI transaction has
already begun on the PCI bus. Target latency rules
require that the data be acquired quickly or that the Tar-
get terminate the transaction with a retry/disconnect.
Also, once the transfer process is underway, the Target
does not know how much more data will be requested,
yet the Target must prefetch data so that it will be avail-
able if needed. Special signals and protocols are
described below to efficiently deal with these unique
demands.
Operation Setup
The FPGA application waits for Target request,
treqn
,
from the PCI core to be active, indicating a Target oper-
ation, either read or write. It then asserts address
enable, taenn, to clock out the command and its
address. Table 40 describes the specific order of oper-
ation for a Target read transaction.
Bursts can be of any length, but will disconnect when
either of the following conditions occur:
I
tr_emptyn
is asserted low.
I
The BAR boundary has been crossed.
Data Transfer
For a target read data transaction, the FPGA applica-
tion begins supplying the requested data by deassert-
ing
taenn
and asserting
trdataenn
. On every cycle that
trdataenn
is asserted, the FPGA application clocks
data into the PCI core’s Target read FIFO (32 deep by
36 bits wide in 32-bit PCI mode; 16 deep by
72 bits wide in 64-bit PCI mode) via bus
trdata
. Since
the Target read FIFO will always be empty at the start
of a transaction, the first Target read request to a spe-
cific address will result in a retry, initiating a delayed
transaction (if signal
trburstpendn
is
deasserted high) or PCI bus wait-states (if signal
trburstpendn
is asserted low).
The signal
trpcihold
can be asserted to hold off activa-
tion of the nonempty condition. While
trpcihold
is
active, the Target read FIFO empty flag will not change
to the nonempty state until it is full, but then will remain
in the nonempty state until that FIFO truly becomes
empty. Use of this signal can result in more efficient uti-
lization of PCI bus bandwidth by causing a full buffer
contents to be burst, without wait-states, whenever the
PCI bus is claimed. This is explained in the Delayed
Transactions section.
FIFO Full/Almost Full
When the Target read FIFO contains four or fewer
empty locations, the PCI core asserts
tr_afulln
, the
almost full indicator. This allows some latency to exist
in the FPGA’s response without risking overfilling the
FIFO. When all locations in the Target read FIFO are
full, the PCI core asserts
tr_fulln
, the full indicator.
Since the data can be simultaneously written to and
read from the Target read FIFO, both
tr_afulln
and
tr_fulln
can change states in either direction multiple
times in the course of a burst data transfer.
FIFO Empty
In addition to the full and almost full signals that report
when the Target read FIFO is currently unable to
receive data from the FPGA application, the PCI core
also provides the FIFO's empty signal. If the FIFO does
go empty, the core will do one of two things. If
twburst-
pendn
is deasserted high, the target will disconnect. If
twburstpendn
is asserted low, the target will assert up
to eight wait-states and then disconnect if still empty.
The FIFO empty flag is not generally used in user
designs. If it is, however, keep in mind that it is synchro-
nous to
pciclk
.
Bursting
Signal
trlastcycn
tells the FPGA application whether
the current read is a burst. One data element must be
supplied regardless of this signal’s state. The FPGA
application continues to supply data elements (contin-
gent on the full bits) as long as
trlastcycn
is inactive.
Note that this may result in the discarding of unused
data elements supplied in excess of the PCI transac-
tion’s needs. Burst transfers are done either as continu-
ous data phases if read data continues to be available
in the read data FIFO, or as a series of transfers termi-
nated as disconnects without data. Bursts will continue
until either
trlastcycn
is received, the BAR
boundary is
crossed, or a 2
18
physical page address is crossed.
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