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參數(shù)資料
| 型號： | OR3LP26B |
| 英文描述： | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）嵌入式主/目標PCI接口 |
| 文件頁數(shù)： | 24/184頁 |
| 文件大?。?/td> | 5590K |
| 代理商： | OR3LP26B |
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ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
24
L Lucent Technologies Inc.
PCI Bus Core Detailed Description
Dual Port
(continued)
Table 8. Embedded Core/FPGA Interface Signals
(continued)
Symbol
I/O
Description
Target FIFO Address and Command Register Control Signals
tfifoclrn
O
Target FIFO Clear.
This active-low signal is asserted by the FPGA Target to
clear all Target FIFOs.
This signal must be synchronous to
fclk
.
Target Request from PCI.
This active-low signal is synchronous to the Target
FIFO clock signal. The PCI core asserts
treqn
as an indication to the Target
that a transfer request (either read or write) is pending to the target. As long as
there are valid target addresses present in the address FIFO, the treqn signal
will continue to be active.
This signal is synchronous to
fclk
.
Target Logic Ready.
This active-high signal indicates that the Target logic inter-
facing to the FPGA logic is ready. This signal will be inactive during PCI bus
reset or Target FIFO clears.
This signal is synchronous to
fclk
.
Target Address and Command Register Output Enable.
This active-low sig-
nal enables PCI addresses to be read from the Target address register of the
PCI core, and PCI commands to be read from the Target command register.
The PCI core will only execute enough address cycles to transfer the address
within the matched page (higher-order bits are not stripped).
This signal must be synchronous to
fclk
.
Target Command Code.
This bus provides the command code for a new Tar-
get operation, and is valid when the FPGA senses
treqn
active-low.
Because it is synchronous to
pciclk
, it must be qualified with
treqn
.
Base Address Register Number.
This bus indicates which of the six BARs
matched the address for the current Target operation, and is valid when the
FPGA senses
treqn
active-low. The three 64-bit BARs are designated as num-
bers 0, 2, and 4.
Because it is synchronous to
pciclk
, it must be qualified with
treqn
.
Internal State Counter.
Used for target reads and writes. Details of the target
state machine operation can be found in tables at the end of each operation
section.
This signal is synchronous to
fclk
.
treqn
I
t_ready
I
taenn
O
tcmd[3:0]
I
bar[2:0]
I
tstatecntr[2:0]
I
Target Write Data FIFO Signals
twdataenn
O
Target Write FIFO Data Enable.
This active-low signal enables data from the
PCI core Target write data FIFOs onto bus
datatofpga
during Target write oper-
ations on the rising edge of the Target FIFO clock signal. Valid data will be read
from the FIFO whenever it is not empty.
This signal must be synchronous to
fclk
.
Target Write FIFO Empty.
This signal active indicates that the Target write
FIFO is empty.
This signal is synchronous to
fclk
.
Target Write FIFO Almost Empty.
This active-low signal indicates that only
four more empty locations are available in the Target write FIFOs.
This signal is synchronous to
fclk
.
Target Write Data FIFO Full Flag
. This active-low signal indicates that the tar-
get write data FIFO is full. Refer to target write description on signal usage.
This signal is synchronous to
pciclk
.
tw_emptyn
I
tw_aemptyn
I
tw_fulln
I
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相關代理商/技術參數(shù) |
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| OR3LP26BBA352-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3LP26BBM680-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T125 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-4BC432I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T125-4BC600I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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