參數(shù)資料
型號(hào)： OR3LP26B
英文描述： Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
中文描述： 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口
文件頁(yè)數(shù)： 6/184頁(yè)
文件大?。?/td> 5590K
代理商： OR3LP26B
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6
LLucent Technologies Inc.
ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
FPSC Highlights
(continued)
— Softwired LUTs (SWL) allow fast cascading of up
to three levels of LUT logic in a single PFU.
— Supplemental logic and interconnect cell (SLIC)
provides 3-statable buffers, up to 10-bit decoder,
and PAL*-like AND-OR-INVERT (AOI) in each
programmable logic cell (PLC).
— Up to three ExpressCLK inputs allow extremely
fast clocking of signals on- and off-chip plus
access to internal general clock routing.
— Dual-use microprocessor interface (MPI) can be
used for configuration, readback, device control,
and device status, as well as for a general-pur-
pose interface to the FPGA. Glueless interface to
i960
and PowerPC
processors with user-config-
urable address space provided.
— Programmable clock manager (PCM) adjusts
clock phase and duty cycle for input clock rates
from 5 MHz to 120 MHz. The PCM may be com-
bined with FPGA logic to create complex func-
tions, such as digital phase-locked loops (DPLL),
frequency counters, and frequency synthesizers
or clock doublers. Two PCMs are provided per
device.
— True
internal 3-state, bidirectional buses with sim-
ple control provided by the SLIC.
— 32 x 4
RAM per PFU, configurable as single or
dual port. Create large, fast RAM/ROM blocks
(128 x 8 in only eight PFUs) using the SLIC
decoders as bank drivers.
— Built-in boundary scan (IEEE
§
1149.1 JTAG) and
TS_ALL testability function to 3-state all I/O pins.
I
High-speed
on-chip interface provided between
FPGA logic and embedded core to reduce bottle-
necks typically found when interfacing off-chip.
I
Supported in two packages: 352-pin PBGA and
680-pin PBGAM.
*
PAL is a trademark of Advanced Micro Devices, Inc.
i960is a registered trademark of Intel Corporation.
PowerPC is a registered trademark of International Business
Machines Corporation.
§ IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Note
: This document will conform to the nomenclature
of the PCI Local Bus Specification, as follows:
Software Support
I
Supported by ORCA Foundry software and third-
party CAE tools for implementing ORCA Series 3+
devices and simulation/timing analysis with embed-
ded PCI bus core.
I
PCI core configuration options and simulation
netlists generated by FPSC Configuration Manager
utility in ORCAFoundry software.
I
Preference files provided for timing interface between
PCI bus core and FPGA logic.
Term
byte
word
DWORD
Quadword
Meaning
8 bits
16 bits
32 bits
64 bits
相關(guān)PDF資料
PDF描述
OR3TP12-6BA256 Single 2.3V 10 MHz OP w/ CS, I temp, -40C to +85C, 8-TSSOP, T/R
OR3TP12-6BA256I Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, TUBE
OR3TP12-6BA352 Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
OR3TP12-6BA352I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR3LP26BBA352-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3LP26BBM680-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3T125 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays
OR3T125-4BC432I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
OR3T125-4BC600I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
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