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| 型號： | OR3LP26B |
| 英文描述： | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）嵌入式主/目標PCI接口 |
| 文件頁數(shù)： | 23/184頁 |
| 文件大小： | 5590K |
| 代理商： | OR3LP26B |
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Lucent Technologies Inc.
Lucent Technologies Inc.
23
Data Sheet
March 2000
ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description
Dual Port
(continued)
Table 8. Embedded Core/FPGA Interface Signals
(continued)
Symbol
mr_aemptyn
I/O
I
Description
Master Read Data FIFO Almost Empty.
This active-low signal indicates that
only four more data locations are available to be read from the Master read data
FIFOs of the PCI core.
This signal is synchronous to
fclk
.
Master Read Data FIFO Full Flag.
This active-low signal indicates that the
Master read data FIFO is full. Refer to Master read description on signal usage.
This signal is synchronous to
pciclk
.
Stop Burst Reads.
This active-low signal is used by the FPGA Master to termi-
nate burst reads before completion. When asserted, it must stay asserted for a
minimum of two
pciclk
periods. When asserted,
fpga_mstopburstn
must stay
asserted until
ma_fulln
goes inactive (high).
This signal must be synchronous to
pciclk
.
Master Read Last Data Cycle.
This active-low signal is asserted to indicate
that the accompanying Master read data is the final data for this operation.
When more than one cycle is required to transfer a complete data word, this
signal is only valid on the last cycle (1
fclk
period).
This signal is synchronous to
fclk
.
mr_fulln
I
fpga_mstopburstn
O
mrlastcycn
I
Target General Signals
disctimerexpn
I
Discard Timer Expired.
This active-low signal, when asserted, indicates that
the discard timer has expired and the core will now treat the retried delayed
transaction as a new transaction. The discard timer is a 15-bit counter which
starts its count when a delayed transaction is started.
This signal is synchronous to
fclk
.
Target Abort.
This active-high signal is asserted by the FPGA Target applica-
tion to abort all future PCI cycles. Once asserted, this signal needs to remain
asserted for a minimum of two
pciclk
cycles.
This signal must be synchronous to
pciclk
.
Assert Retry.
This active-low signal is asserted by an FPGA Target to the PCI
core to send a retry to the PCI bus. Once asserted, this signal needs to remain
asserted for a minimum of two
pciclk
cycles.
This signal must be synchronous to
pciclk
.
Target Delayed Transaction.
Used for Target I/O write (page 50) and Target
read operations (page 59). Target memory writes are always posted. Once
asserted, this signal needs to remain asserted for a minimum of two
pciclk
cycles.
This signal must be synchronous to
pciclk
.
tcfgshiftenn
is an active-low signal that determines the data that is output by
the PCI core onto signal
pci_tcfg_stat
:
tcfgshiftenn
= 1:
pci_tcfg_stat
= wired-OR of all bits below, after being
masked by FPGA configuration RAM bits;
tcfgshiftenn
= 0:
pci_tcfg_stat
= each bit below, one at a time on suc-
cessive pciclk rising edges (unmasked), reset when
tcfgshiftenn
= 1;
Status bits:
Target abort signaled, system error signaled,
and parity error detected.
Both signals are synchronous to
fclk
.
fpga_tabort
O
fpga_tretryn
O
deltrn
O
tcfgshiftenn
pci_tcfg_stat
O
I
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