參數(shù)資料
型號： OR3LP26B
英文描述： Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口
文件頁數(shù)： 5/184頁
文件大?。?/td> 5590K
代理商： OR3LP26B
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Lucent Technologies Inc.
Lucent Technologies Inc.
5
Data Sheet
March 2000
ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Highlights
(continued)
I
Master:
— Generates all defined command codes except
interrupt acknowledge and special cycle.
— Capable of accessing its own local Target.
— Capable of acting as the system's configuration
agent by booting up with the Master logic
enabled.
— Supports multiple options for Master bus requests,
to increase PCI bus bandwidth.
— Supports single-cycle I/O space accesses.
— Provides option to delay PCI access until FIFO is
full on Master writes to increase PCI bandwidth.
— Supports programmable latency timer control.
I
Target:
— Responds legally to all command codes: interrupt
acknowledge, special cycle, and reserved com-
mands ignored; memory read multiple and line
handled as memory read; memory write and
invalidate handled as memory write.
— Implements Target abort, disconnect, retry, and
wait cycles.
— Handles delayed transactions.
— Handles fast back-to-back transactions.
— Method of handling retries is programmable at
FPGA configuration to allow tailoring to different
Target data access latencies.
— Decodes at medium speed.
— Provides option to delay PCI access until FIFO is
full on Target reads to increase PCI bandwidth.
I
Supports dual-address cycles (both as Master and
Target).
I
Supports all six base address registers (BARs), as
either memory (32-bit or 64-bit) or I/O. Any legal
page size can be independently specified for each
BAR during FPGA configuration.
I
Independent Master and Target clocks can be sup-
plied to the PCI FIFO interface from the FPGA-based
logic.
I
Provides versatile clocking capabilities with FPGA
clocks sourced from PCI bus clock or elsewhere.
FIFO interface buffers asynchronous clock domains
between the PCI interface and FPGA-based logic.
I
PCI interface timing: meets or exceeds 33 MHz,
50 MHz, and 66 MHz PCI requirements.
I
Configuration options:
— Class code, revision ID.
— Latency timer.
— Cache line size.
— Subsystem ID.
— Subsystem vendor ID.
— Maximum latency, minimum grant.
— Interrupt line.
— Hot Plug/Hot Swap capability.
I
Generates interrupts on
intan
as directed by the
FPGA.
I
PCI I/O output drivers can be programmed for fast or
slew-limited operation.
I
Automatically detects 5 V or 3.3 V PCI bus signaling
environment and provides appropriate I/O signaling,
under 3.3 V commercial conditions.
I
Ideally suited for such applications as:
— PCI-based graphics/video/multimedia.
— Bridges to ISA/EISA/MCA, LAN, SCSI, Ethernet,
ATM, or other bus architectures.
— High-bandwidth data transfer in proprietary sys-
tems.
FPSC Highlights
I
Implemented as an embedded core into the
advanced Series 3+ ORCA FPSC architecture.
I
Allows the user to integrate the core with up to 120K
gates of programmable logic, all in one device, and
provides up to 259 user I/O pins in addition to the
PCI interface pins.
I
FPGA portion retains all of the features of the ORCA
3 FPGA architecture:
— High-performance, cost-effective, 0.25 μm
5-level metal technology.
— Twin-quad programmable function unit (PFU)
architecture with eight 16-bit look-up tables
(LUTs) per PFU, organized in two nibbles for use
in nibble- or byte-wide functions. Allows for mixed
arithmetic and logic functions in a single PFU.
Parameter
33 MHz
11.0 ns
7.0 ns
10.0 ns
2.0 ns
30.0 ns
50 pF
50 MHz
7.5 ns
4.5 ns
6.5 ns
1.5 ns
20.0 ns
50 pF
66 MHz
6.0 ns
3.0 ns
5.0 ns
1.0 ns
15.0 ns
10 pF
Device Clock = > Out
Device Setup Time
Board Prop. Delay
Board Clock Skew
Total Budget
Load Capacitance
相關(guān)PDF資料
PDF描述
OR3TP12-6BA256 Single 2.3V 10 MHz OP w/ CS, I temp, -40C to +85C, 8-TSSOP, T/R
OR3TP12-6BA256I Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, TUBE
OR3TP12-6BA352 Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
OR3TP12-6BA352I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR3LP26BBA352-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3LP26BBM680-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3T125 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays
OR3T125-4BC432I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
OR3T125-4BC600I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
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