參數(shù)資料
型號(hào)： OR3LP26B
英文描述： Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
中文描述： 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口
文件頁(yè)數(shù)： 133/184頁(yè)
文件大?。?/td> 5590K
代理商： OR3LP26B
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Lucent Technologies Inc.
Lucent Technologies Inc.
133
Data Sheet
March 2000
ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
Powerup Sequencing for Series OR3LP26B Device
ORCA Series OR3LP26B device use two power supplies: one to power the device I/Os and the ASIC core (V
DD
)
which is set to 3.3 V for 3.3 V operation and 5 V tolerance, and another supply for the internal FPGA logic (V
DD
2)
which is set to 2.5 V. It is understood that many users will derive the 2.5 V core logic supply from a 3.3 V power
supply, so the following recommendations are made as to the powerup sequence of the supplies and allowable
delays between power supplies reaching stable voltages.
In general, both the 3.3 V and the 2.5 V supplies should ramp-up and become stable as close together in time as
possible. There is no delay requirement if the V
DD
2 (2.5 V) supply becomes stable prior to the V
DD
(3.3 V) supply.
There is a delay requirement imposed if the V
DD
supply becomes stable prior to the V
DD
2 supply.
The requirement is that the V
DD
2 (2.5 V) supply transition from 0 V to 2.3 V within 15.7 ms if the V
DD
(3.3 V) supply
is already stable at a minimum of 3.0 V. If the V
DD
supply has not yet reached 3.0 V when the V
DD
2 supply has
reached 2.3 V, then the requirement is that the V
DD
2 supply reach a minimum of 2.3 V within 15.7 ms of when the
V
DD
supply reaches 3.0 V.
If the chosen power supplies cannot meet this delay requirement, it is always possible to hold-off configuration of
the FPGA by asserting INIT or PRGM until the V
DD
2 supply has reached 2.3 V. This process eliminates any power
supply sequencing issues.
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-
lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess
of those given in the operations sections of this data sheet. Exposure to absolute maximum ratings for extended
periods can adversely affect device reliability.
The ORCA Series 3+ FPSCs include circuitry designed to protect the chips from damaging substrate injection cur-
rents and to prevent accumulations of static charge. Nevertheless, conventional precautions should be observed
during storage, handling, and use to avoid exposure to excessive electrical stress.
Table 46. Absolute Maximum Ratings
Note: For PCI bus signals used for 5 V signaling and FPGA inputs used as 5 V tolerant, the maximum value is 5.8 V.
Parameter
Symbol
Min
Max
Unit
Storage Temperature
I/O and ASIC Supply Voltage with Respect to
Ground
Internal FPGA Supply Voltage with Respect
to Ground
Input Signal with Respect to Ground
CMOS Inputs
5 V Tolerant Inputs
Signal Applied to High-impedance Output
T
stg
V
DD
–65
—
150
≤
4.2
°C
V
V
DD
2
—
≤
3.2
V
—
—
—
–0.5
–0.5
–0.5
V
DD
+ 0.3
5.8
V
DD
+ 0.3
V
V
V
相關(guān)PDF資料
PDF描述
OR3TP12-6BA256 Single 2.3V 10 MHz OP w/ CS, I temp, -40C to +85C, 8-TSSOP, T/R
OR3TP12-6BA256I Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, TUBE
OR3TP12-6BA352 Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
OR3TP12-6BA352I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR3LP26BBA352-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3LP26BBM680-DB 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3T125 制造商:AGERE 制造商全稱(chēng):AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays
OR3T125-4BC432I 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Field Programmable Gate Array (FPGA)
OR3T125-4BC600I 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Field Programmable Gate Array (FPGA)
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