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參數(shù)資料
| 型號： | OR3LP26B |
| 英文描述： | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）嵌入式主/目標PCI接口 |
| 文件頁數(shù)： | 130/184頁 |
| 文件大小： | 5590K |
| 代理商： | OR3LP26B |
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130
LLucent Technologies Inc.
ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
FPGA Configuration Data Format
The ORCAFoundry development system interfaces
with front-end design entry tools and provides tools to
produce a fully configured FPSC. This section dis-
cusses using the ORCA Foundry development system
to generate configuration RAM data and then provides
the details of the configuration frame format.
Using ORCAFoundry to Generate
Configuration RAM Data
The configuration data bit stream defines the PCI
embedded core configuration, the FPGA logic function-
ality, and the I/O configuration and interconnection. The
data bit stream is generated by the ORCAFoundry
development tools. The bit stream created by the bit
stream generation tool is a series of 1s and 0s used to
write the FPSC configuration RAM. It can be loaded
into the FPSC using one of the configuration modes
discussed elsewhere in this data sheet.
For FPSCs, the bit stream is prepared in two separate
steps in the design flow. The configuration options of
the embedded core are specified using ORCA
OR3LP26B Design Kit Software at the beginning of the
design process. This offers the designer a specific con-
figuration to simulate and design the FPGA logic to.
Upon completion of the design, the bit stream genera-
tor combines the embedded core options and the
FPGA configuration into a single bit stream for down-
load into the FPSC.
FPGA Configuration Data Frame
Configuration data can be presented to the FPSC in
two frame formats: autoincrement and explicit. A
detailed description of the frame formats is shown in
Figure 49, Figure 50, and Table 43. The two modes are
similar except that autoincrement mode uses assumed
address incrementation to reduce the bit stream size,
and explicit mode requires an address for each data
frame. In both cases, the header frame begins with a
series of 1s and a preamble of 0010, followed by a
24-bit length count field representing the total number
of configuration clocks needed to complete the loading
of the FPSC.
The mandatory ID frame contains data used to deter-
mine if the bit stream is being loaded to the correct type
of ORCA
device (i.e., a bit stream generated for an
OR3LP26B is being sent to an OR3LP26B). Error
checking is always enabled for Series 3+ devices,
through the use of an 8-bit checksum. One bit in the ID
frame also selects between the autoincrement and
explicit address modes for this load of the configuration
data.
A configuration data frame follows the ID frame. A data
frame starts with a one-start bit pair and ends with
enough one-stop bits to reach a byte boundary. If using
autoincrement configuration mode, subsequent data
frames can follow. If using explicit mode, one or more
address frames must follow each data frame, telling the
FPSC at what addresses the preceding data frame is to
be stored (each data frame can be sent to multiple
addresses).
Following all data and address frames is the postam-
ble. The format of the postamble is the same as an
address frame with the highest possible address value
with the checksum set to all ones.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3LP26BBA352-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3LP26BBM680-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T125 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-4BC432I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T125-4BC600I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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