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參數(shù)資料
| 型號： | OR3LP26B |
| 英文描述： | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口 |
| 文件頁數(shù)： | 74/184頁 |
| 文件大?。?/td> | 5590K |
| 代理商： | OR3LP26B |
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ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
74
L Lucent Technologies Inc.
PCI Bus Core Detailed Description
Quad Port
(continued)
Table 23. Embedded Core/FPGA Interface Signals
(continued)
Symbol
tw_aemptyn
I/O
I
Description
Target Write FIFO Almost Empty.
This active-low signal indicates that only four
more empty locations are available in the Target write FIFOs.
This signal is synchronous to
fclk
.
Target Write Data FIFO Full Flag
. This active-low signal indicates that the target
write data FIFO is full. Refer to target write description on signal usage.
This signal is synchronous to
pciclk
.
Target Write Last Data Cycle.
This active-low signal has two functions:
a. It is asserted low to indicate that the accompanying 32/64 bits of Target read or
write address information is the final portion being sent. It can also be asserted
prior to any address portion being sent, indicating that the previous address is
to be used.
b. It is asserted low to indicate that the accompanying Target write data is the final
data for this operation. When more than one cycle is required to transfer a com-
plete data word, this signal is only valid on the last cycle.
This signal is synchronous to
fclk
.
Target Write Burst Data Availability Pending Flag.
This active-low signal
directs the PCI core not to immediately disconnect when the Target write FIFO
becomes full, but rather to insert PCI bus wait-states (up to the maximum allowed,
and then disconnect). Once asserted, this signal needs to remain asserted for a
minimum or two
pciclk
periods.
This signal must be synchronous to
pciclk
.
Target Read Data FIFO Signals
trdataenn
O
Target Read FIFO Data Enable.
This active-low signal enables the registering of
bus
datafmfpga
during Target read operations into the PCI core Target read data
FIFOs on the rising edge of the Target FIFO clock signal. The signal
trdataenn
should not be asserted when the Target read data FIFOs are full, or data may be
lost.
This signal must be synchronous to
fclk
.
tr_fulln
I
Target Read FIFO Full.
This signal is active-low and synchronous to the rising
edge of the Target FIFO clock signal. The PCI core asserts this signal to indicate
that the Target read FIFOs are full and that no more data can be clocked in.
This signal is synchronous to
fclk
.
tr_afulln
I
Target Read FIFO Almost Full.
This active-low signal indicates that the Target
read FIFO has only four more empty locations available in the FIFOs.
This signal is synchronous to
fclk
.
tr_emptyn
I
Target Read Data FIFO Empty Flag.
This active-low signal indicates that the tar-
get read data FIFO is empty. Refer to target read description on signal usage.
This signal is synchronous to
pciclk
.
trpcihold
O
Target Read PCI Bus Hold
. During burst transfers on the PCI bus, this signal
delays the start of the transfer on the PCI bus, allowing the FPGA application to fill
the FIFO. The transaction will begin when
trpcihold
is deasserted or the FIFO
becomes full. Once asserted, this signal needs to remain asserted for a minimum
or two
pciclk
periods.
This signal must be synchronous to
pciclk
.
tw_fulln
I
twlastcycn
I
twburstpendn
O
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| OR3LP26BBA352-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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