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參數(shù)資料
| 型號(hào)： | OR3LP26B |
| 英文描述： | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| 中文描述： | 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口 |
| 文件頁數(shù)： | 137/184頁 |
| 文件大小： | 5590K |
| 代理商： | OR3LP26B |
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Lucent Technologies Inc.
Lucent Technologies Inc.
137
Data Sheet
March 2000
ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
Timing Characteristics
(continued)
In addition to supply voltage, process variation, and operating temperature, circuit and process improvements of
the ORCA Series FPGAs over time will result in significant improvement of the actual performance over those
listed for a speed grade. Even though lower speed grades may still be available, the distribution of yield to timing
parameters may be several speed grades higher than that designated on a product brand. Design practices need
to consider best-case timing parameters (e.g., delays = 0), as well as worst-case timing.
The routing delays are a function of fan-out and the capacitance associated with the CIPs and metal interconnect
in the path. The number of logic elements that can be driven (fan-out) by PFUs is unlimited, although the delay to
reach a valid logic level can exceed timing requirements. It is difficult to make accurate routing delay estimates
prior to design compilation based on fan-out. This is because the CAE software may delete redundant logic
inserted by the designer to reduce fan-out, and/or it may also automatically reduce fan-out by net splitting.
The waveform test points are given in the Input/Output Buffer Measurement Conditions section of this data sheet.
The timing parameters given in the electrical characteristics tables in this data sheet follow industry practices, and
the values they reflect are described below.
Propagation Delay
—The time between the specified reference points. The delays provided are the worst case of
the tphh and tpll delays for noninverting functions, tplh and tphl for inverting functions, and tphz and tplz for 3-state
enable.
Setup Time
—The interval immediately preceding the transition of a clock or latch enable signal, during which the
data must be stable to ensure it is recognized as the intended value.
Hold Time
—The interval immediately following the transition of a clock or latch enable signal, during which the
data must be held stable to ensure it is recognized as the intended value.
3-State Enable
—The time from when a 3-state control signal becomes active and the output pad reaches the
high-impedance state.
Clock Timing
Table 51.
ExpressCLK
(ECLK) and Fast Clock (fclk) Timing Characteristics
OR3LP26B Commercial: V
DD
= 3.0 V to 3.6 V, 0 °C
<
T
A
<
70 °C; V
DD2
= 2.38 V to 2.63 V, 0 °C
<
T
A
<
70 °C.
Notes:
The
ECLK
delays are to all of the PICs on one side of the device for middle pin input, or two sides of the device for corner pin input. The delay
includes both the input buffer delay and the clock routing to the PIC clock input.
The
fclk
delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network. It includes both the input buffer delay
and the clock routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used.
Device
(T
J
= 85 °C, V
DD
= min)
Symbol
Min
Max
Unit
ECLK Delay (middle pad)
ECLK Delay (corner pad)
fclk Delay (middle pad)
fclk Delay (corner pad)
eclkm_del
eclkc_del
fclkm_del
fclkc_del
—
—
—
—
1.99
4.20
5.24
7.46
ns
ns
ns
ns
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| OR3LP26BBA352-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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| OR3T125 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-4BC432I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T125-4BC600I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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