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| 型號(hào)： | OR3LP26B |
| 英文描述： | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| 中文描述： | 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口 |
| 文件頁(yè)數(shù)： | 152/184頁(yè) |
| 文件大?。?/td> | 5590K |
| 代理商： | OR3LP26B |
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ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
152
L Lucent Technologies Inc.
Pin Information
(continued)
Table 68.
FPGA Common-Function Pin Descriptions
(continued)
* The ORCA Series 3 FPGA data sheet contains more information on how to control these signals during start-up. The timing of DONE release
is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all
user I/Os) is controlled by a second set of options.
Symbol
I/O
Description
Special-Purpose Pins
(continued)
TDI, TCK, TMS
I
If boundary scan is used, these pins are test data in, test clock, and test mode select
inputs. If boundary scan is not selected, all boundary-scan functions are inhibited
once configuration is complete. Even if boundary scan is not used, either TCK or
TMS must be held at logic 1 during configuration. Each pin has a pull-up enabled
during configuration.
After configuration, these pins are user-programmable I/O.*
During configuration in peripheral mode, RDY/RCLK indicates another byte can be
written to the FPGA. If a read operation is done when the device is selected, the
same status is also available on D7 in asynchronous peripheral mode.
During the Master parallel configuration mode, RCLK is a read output signal to an
external memory. This output is not normally used.
In i960microprocessor mode, this pin acts as the address latch enable (ALE) input.
After configuration, if the
MPI
is not used, this pin is a user-programmable I/O pin.*
High During Configuration is output high until configuration is complete. It is used as
a control output indicating that configuration is not complete.
Low During Configuration is output low until configuration is complete. It is used as a
control output indicating that configuration is not complete.
I/O
O
RDY/RCLK/
MPI_ALE
O
I
I/O
O
HDC
LDC
O
INIT
I/O
INIT
is a bidirectional signal before and during configuration. During configuration, a
pull-up is enabled, but an external pull-up resistor is recommended. As an active-
low open-drain output,
INIT
is held low during power stabilization and internal clear-
ing of memory. As an active-low input,
INIT
holds the FPGA in the wait-state before
the start of configuration.
CS0
and CS1 are used in the asynchronous peripheral, slave parallel, and micropro-
cessor configuration modes. The FPGA is selected when
CS0
is low and CS1 is
high. During configuration, a pull-up is enabled.
After configuration, these pins are user-programmable I/O pins.*
CS0
, CS1
I
I/O
I
RD
/
MPI_STRB
RD
is used in the asynchronous peripheral configuration mode. A low on
RD
changes D7 into a status output. As a status indication, a high indicates ready, and a
low indicates busy.
WR
and
RD
should not be used simultaneously. If they are, the
write strobe overrides.
This pin is also used as the microprocessor interface (
MPI
) data transfer strobe. For
PowerPC it is the transfer start (TS). For i960, it is the address/data strobe (
ADS
).
After configuration, if the
MPI
is not used, this pin is a user-programmable I/O pin.*
I
I/O
I
WR
WR
is used in the asynchronous peripheral configuration mode. When the FPGA is
selected, a low on the write strobe,
WR
, loads the data on D[7:0] inputs into an
internal data buffer.
WR
and
RD
should not be used simultaneously. If they are, the
write strobe overrides.
After configuration, this pin is a user-programmable I/O pin.*
I/O
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| OR3LP26BBA352-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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| OR3T125 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-4BC432I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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