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參數(shù)資料
| 型號(hào)： | OR3LP26B |
| 英文描述： | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口 |
| 文件頁數(shù)： | 86/184頁 |
| 文件大?。?/td> | 5590K |
| 代理商： | OR3LP26B |
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ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
86
L Lucent Technologies Inc.
PCI Bus Core Detailed Description Quad Port
(continued)
Embedded Core/FPGA Interface Operation
Dual Master Address Holding Registers
The PCI core utilizes a pair of address holding registers to reduce latency when setting up repeated Master trans-
fers to or from the same address. Every Master operation has associated with it one of the two holding registers, as
specified by the holding register selector signal (as described in Table 25). Each address holding register records
the full previous address, allowing some, all, or none of that recorded address to be used to build the next address
associated with that holding register. This can save up to two cycles for quad-port mode. The holding register
optionally supplies the most significant portion, or all, or none, of the address. The amount supplied by the holding
register is determined by the timing of the signal
mwlastcycn
, which accompanies the last portion of data, or
accompanies the command word when the holding register supplies the entire address. Table 34 below gives
examples in quad-port, 64-bit addressing mode, of typical operation using the holding registers, illustrating the
above rules.
The two holding registers can be assigned one to read and one to write, thus providing two unrelated areas for the
two functions. Another useful application is to dedicate one register to a fixed address such as the beginning of a
buffer, the data port of a FIFO or a mailbox register. This especially increases effective bandwidth on shorter bursts.
Table 34. Holding Registers, Examples of Typical Operation
Target Address Holding Register and BAR Number Indicator
The PCI core provides two features that reduce overhead on setup of Target transfers in quad-port 64-bit address-
ing mode.
First, the PCI core’s Target control logic detects the page size of the base address register (BAR) that matched the
current PCI address, and only transfers the address bytes necessary to send the page address, and not the virtual
address of the page, to the FPGA application. The
bar
bus is synchronous to the
pciclk
, so it must be qualified with
treq
which is on the
fclk
clock domain.
Second, the PCI core utilizes an optional address holding register so that only the least significant portion of the
address that is different from the previous address is sent to the FPGA application. Utilization of this feature usually
reduces the amount of address that must be transferred, but may require that the FPGA application build a copy of
the holding register in order to reconstruct the address. For this reason, this feature is optional and can be disabled
via a bit in the FPGA configuration manager.
Address on Bus
mwdata
Last
Cycle
Valid
With
Holding
Register
Select
Holding Register 0
Initial Value
Holding Register 1
Initial Value
Master Read/Write
Address
AU
AL
AU
AL
AU
AL
AU
AL
1111-1111 2222-2222
—
4444-4444 5555-5555
—
—
—
—
8888-8888 9999-9999
AU
AL
AU
Cmd
AL
Cmd
AL
AU
0
0
1
0
0
1
1
0
xxxx-xxxx
1111-1111 2222-2222
1111-1111 3333-3333
1111-1111 3333-3333 4444-4444 5555-5555 1111-1111 3333-3333
1111-1111 3333-3333 4444-4444 5555-5555 1111-1111 6666-6666
1111-1111 6666-6666 4444-4444 5555-5555 4444-4444 5555-5555
1111-1111 6666-6666 4444-4444 5555-5555 4444-4444 7777-7777
1111-1111 6666-6666 4444-4444 7777-7777 8888-8888 9999-9999
xxxx-xxxx
xxxx-xxxx
xxxx-xxxx
xxxx-xxxx
xxxx-xxxx
xxxx-xxxx
xxxx-xxxx
1111-1111 2222-2222
1111-1111 3333-3333
4444-4444 5555-5555
3333-3333
—
6666-6666
—
7777-7777
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