參數(shù)資料
型號： OR3LP26B
英文描述： Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）嵌入式主/目標PCI接口
文件頁數(shù)： 25/184頁
文件大小： 5590K
代理商： OR3LP26B
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Lucent Technologies Inc.
Lucent Technologies Inc.
25
Data Sheet
March 2000
ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description
Dual Port
(continued)
Table 8. Embedded Core/FPGA Interface Signals
(continued)
Symbol
twlastcycn
I/O
I
Description
Target Write Last Data Cycle.
This active-low signal has two functions:
a. It is asserted low to indicate that the accompanying 32/64 bits of Target read or
write address information is the final portion being sent. It can also be asserted
prior to any address portion being sent, indicating that the previous address is
to be used.
b. It is asserted low to indicate that the accompanying Target write data is the final
data for this operation. When more than one cycle is required to transfer a com-
plete data word, this signal is only valid on the last cycle.
This signal is synchronous to
fclk
.
Target Read Data FIFO Signals
twburstpendn
O
Target Write Burst Data Availability Pending Flag.
This active-low signal
directs the PCI core not to immediately disconnect when the Target write FIFO
becomes full, but rather to insert PCI bus wait-states (up to the maximum allowed,
and then disconnect). Once asserted, this signal needs to remain asserted for a
minimum of two
pciclk
periods.
This signal must be synchronous to
pciclk
.
trdataenn
O
Target Read FIFO Data Enable.
This active-low signal enables the registering of
bus
datafmfpga
during Target read operations into the PCI core Target read data
FIFOs on the rising edge of the Target FIFO clock signal. The signal
trdataenn
should not be asserted when the Target read data FIFOs are full, or data may be
lost.
This signal must be synchronous to
fclk
.
tr_fulln
I
Target Read FIFO Full.
This signal is active-low and synchronous to the rising
edge of the Target FIFO clock signal. The PCI core asserts this signal to indicate
that the Target read FIFOs are full and that no more data can be clocked in.
This signal is synchronous to
fclk
.
tr_afulln
I
Target Read FIFO Almost Full.
This active-low signal indicates that the Target
read FIFO has only four more empty locations available in the FIFOs.
This signal is synchronous to
fclk
.
tr_emptyn
I
Target Read Data FIFO Empty Flag.
This active-low signal indicates that the tar-
get read data FIFO is empty. Refer to target read description on signal usage.
This signal is synchronous to
pciclk
.
trpcihold
O
Target Read PCI Bus Hold
. During burst transfers on the PCI bus, this signal
delays the start of the transfer on the PCI bus, allowing the FPGA application to fill
the FIFO. The transaction will begin when
trpcihold
is deasserted or the FIFO
becomes full. Once asserted, this signal needs to remain asserted for a minimum
of two
pciclk
periods.
This signal must be synchronous to
pciclk
.
trlastcycn
I
Target Read Last Data Cycle.
This active-low signal is asserted to indicate that
the accompanying Target read data is the final data for this operation. When more
than one cycle is required to transfer a complete data word, this signal is only
valid on the last cycle. During a read burst,
trlastcycn
may remain inactive for
longer than it is required to complete the data transfer. If this occurs, the FPGA
Target should continue to write data into the Target read FIFOs unless the incre-
mented address crosses the address decode space of the FPGA Target. The
address should be incremented by a double word as long as
trlastcycn
is inac-
tive.
This signal is synchronous to
fclk
.
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