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參數(shù)資料
| 型號(hào)： | OR3LP26B |
| 英文描述： | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| 中文描述： | 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口 |
| 文件頁數(shù)： | 87/184頁 |
| 文件大?。?/td> | 5590K |
| 代理商： | OR3LP26B |
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Lucent Technologies Inc.
Lucent Technologies Inc.
87
Data Sheet
March 2000
ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description Quad Port
(continued)
Interrupt Request and System Error Generation
Two additional signals are available on the user side interface to request an interrupt on
intan
(
pci_intan
) and
force a system error on the PCI
serrn
pin (
fpga_syserror
). The
pci_intan
signal may be asserted low at any time.
It is not directly tied to any bus cycle. The
fpga_syserror
, as well, may be asserted high at any time. The
serrn
will
be subsequently asserted low during the next PCI transaction to this device. In generating
pci_intan
and
fpga_syserror
, keep in mind that both signals need to be synchronous to
pciclk
.
Working in 32- and 64-bit Modes
The OR3LP26B works equally well in 32-bit and 64-bit PCI systems. In a 64-bit system, it is required that, during
reset, the host assert
req64n
low indicating that the bus width is 64 bits. The core will evaluate this signal at reset,
and automatically configure itself in either 32-bit or 64-bit mode. When configured in 32-bit mode, the core will 3-
state all upper PCI bus pins and apply a weak pull-up.
32-bit Transfers in a 64-bit System
Although designed as a 64-bit interface, the OR3LP26B also works efficiently in 32-bit mode. For single 32-bit
transfers, the core will perform a 32-bit PCI transfer. For burst transactions, the core will attempt 64-bit transfers,
and then back down to 32-bit mode if
ack64n
was not received. In general, the core will perform the PCI bus trans-
action that is most efficient on the bus.
Embedded Core/FPGA Interface Operation Summary
The following sections describe the FIFO bus operation, which is the interface between the embedded core and the
FPGA logic. Several configurations are possible for the FIFO bus, and the signal definitions can change for differ-
ent modes. Tables are provided to define the modes, the signal definitions, and the states of each operation for
each mode.
Table 35 is an index to the state tables and timing figures provided for each of the operational modes of the FPGA
interface to the PCI core. Each of these operations is detailed on the pages shown in the table.
Table 35. Index to State Sequence Tables
* Duplicate burst length and 16-bit address.
64-bit address supplied.
32-bit address supplied.
§The FPGA interface does not participate in Target configuration operations.
Master/
Target
Master
PCI Bus
Mode
Write
Transaction Type
Single/Burst and Delayed/
Not Delayed
Nonburst
Burst
Nonburst
Burst
Nonburst
Delayed
Nonburst, Not Delayed
Burst
Nonburst
Delayed
Not Delayed
Nonburst
Nonburst Delayed
Burst
Burst Delayed
PCI Bus Timing
Figure Number
Figure 25
Figure 26
Figure 29
Figure 31
Figure 33
Figure 34
Figure 35
Figure 37
Figure 39
Figure 40
Figure 41
Figure 44
Figure 42
Figure 47
Figure 45
State Table
FPGA Bus Timing
Figure Number
Figure 27
Figure 28
Figure 30
Figure 32
§
Config,
Memory, I/O
Config,
Memory, I/O
Config
I/O
Memory, I/O
Memory
Config
I/O
Table 36
Read
Table 37*
Table 38
Table 39
Target
Write
Figure 36
Figure 38
Read
Table 40
§
Figure 43
Memory
Figure 46
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| OR3LP26BBA352-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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| OR3T125 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-4BC432I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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