參數(shù)資料
型號： OR3LP26B
英文描述： Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）嵌入式主/目標PCI接口
文件頁數(shù)： 128/184頁
文件大?。?/td> 5590K
代理商： OR3LP26B
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128
LLucent Technologies Inc.
ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
Clocking Options at FPGA/Core
Boundary
The OR3LP26B supports a wide variety of integrated
FPGA/core clocking schemes which, in conjunction
with the FIFO interfaces between the PCI bus and the
FPGA, gives the designer many flexible options.
The Master and Target FIFOs are independently
clocked on the FPGA side by either
fclk1
or
fclk2
. The
clocks used for the Master FIFO and Target FIFO inter-
faces to the FPGA logic are independent when the
interface is configured in quad-port mode, but they
must be tied to the same clock signal for dual-port
mode.
Figure 48 illustrates the special clock paths provided to
service the clocking needs of PCI functions. The vari-
ous clocking options shown in Figure 48 are discussed
below.
Although there are many clocking options, minimum
clock skew is obtained by following the following recom-
mendations. This section is divided into internally gen-
erated clocks, external system clocks, external express
clocks, and external corner clocks that utilize the PLLs.
Refer to the Series 3L data sheet and application notes
for a full description of all of the clocking options avail-
able for the Series 3L parts.
PCI Clock as System Clock
The clock received from the PCI interface can be
brought across the PCI core into the FPGA logic sec-
tion and used as the clock for the entire FPSC, or even
as the clock for the entire board on which the FPSC
resides. It is important that this signal be available via
the PCI core since PCI rules allow for only one load per
agent on the PCI bus clock. The FPSC incorporates
special clock lines for the purpose of distributing the
PCI clock; these lines are hard-connected to the PCI
core's circuitry but can also be passed up onto the
FPGA portion's clock grid. From there, in addition to
feeding clocks to all PFUs and PIOs, this clock can also
drive the clock inputs to the FPGA side of the Master
and/or Target FIFOs, and can be made available off-
chip.
Local Clock as System Clock
The FIFO-buffered interface between the PCI logic and
the FPGA allows other clocks to be utilized in the
FPGA as well. The Master and Target interfaces each
have independent clock nets and can be connected to
the same or separate clocks. Essentially, this means
that both the Master and Target logic and FIFOs can be
independently set to use the PCI clock or another
clock. Clocks can be fed from any I/O pad, from
express clock inputs, or from internal logic, and can be
fed via the programmable clock manager (PCM).
Internally Generated Clocks
I
There are no limitations for using 1 or 2 internally
generated clocks to connect to the
fclk1
and/or
fclk2
clock input pins.
External System Clocks
External system clocks are clock inputs that do not use
the three dedicated
eclk
input clock pins of the device.
I
Keep the clocks toward the center of a side instead
of in the corners for minimal skew across the FPGA.
I
The best skew across the FPGA/ASIC boundary is
obtained by selecting pins on the left or right side of
the die. Avoid using general I/O as clock inputs on
the top of the device.
I
Refer to the Series 3 clocking application note for
general FPGA clocking rules.
External Express Clocks
External express clocks are externally generated
clocks that enter on one of the three eclk pins of the
device.
I
The best skew across the FPGA/ASIC boundary is
obtained by selecting the
eclk
pin on the right side of
the device (
eclkr
). Avoid using the top or left side
eclk
inputs.
Externally Generated Clocks Entering Through
PCM Input Pins
External PCM clocks are clocks entering and going
through the programmable clock managers.
I
When using a programmable clock manager, either
the upper right or lower left clock managers may be
used.
Clock Sourced from pciclk
I
There are no limitations for using the
pciclk
clock
output to connect to the
fclk1
and/or
fclk2
clock
input pins.
相關PDF資料
PDF描述
OR3TP12-6BA256 Single 2.3V 10 MHz OP w/ CS, I temp, -40C to +85C, 8-TSSOP, T/R
OR3TP12-6BA256I Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, TUBE
OR3TP12-6BA352 Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
OR3TP12-6BA352I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
相關代理商/技術參數(shù)
參數(shù)描述
OR3LP26BBA352-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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