參數(shù)資料
型號(hào)： OR3LP26B
英文描述： Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
中文描述： 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口
文件頁(yè)數(shù)： 20/184頁(yè)
文件大?。?/td> 5590K
代理商： OR3LP26B
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ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
20
L Lucent Technologies Inc.
PCI Bus Core Detailed Description
(continued)
Table 7. PCI Bus Pin Descriptions
(continued)
Symbol
serrn
I/O
O
Description
System Error.
An active-low open drain signal pulsed by agents to report errors
other than parity.
serrn
is sampled every
clk
edge, so any agent asserting
serrn
must ensure it is valid for at least one clock period. The OR3LP26B asserts
serrn
if
a Master abort sequence is asserted when the Master controller is accessing the
PCI bus.
Interrupt Pins
intan
O
PCI Interrupt.
The OR3LP26B asserts this active-low open drain signal when it
requests an interrupt from the PCI compliant interrupt controller.
64-Bit Bus Extension Pins
ad[63:32]
I/O
64-Bit Address and Data.
These signals provide the upper 32 bits of address and
data when in PCI 64-bit operation. During an address phase (when using the DAC
command and when
req64n
is asserted), these address bits are transferred. Dur-
ing a data phase, the data is valid when
req64n
and
ack64n
are both asserted.
Otherwise, these bits are 3-stated.
Byte Enables.
These are the upper four, active-low, bus command and byte
enables when in PCI 64-bit operation. During an address phase (when using the
DAC command and when
req64n
is asserted), the bus command is transferred.
During a data phase, these bits are the active-low byte enables for data bits 64:32.
Otherwise, these bits are 3-stated.
Request 64-Bit Transfer.
This active-low signal is asserted by the current bus
Master to indicate that it desires to transfer data using 64 bits. The signal
req64n
has the same meaning as
framen
for 32-bit transfers.
Acknowledge 64-Bit Transfer.
The Target drives this signal low to indicate that it
has decoded its own address as the Target of the current access and that it can do
64-bit transfers. The signal
ack64n
has the same timing as
devseln
in 32-bit trans-
fers.
Upper Double-Word Parity.
The even parity bit that covers
ad[63:32]
and
c_ben[7:4]
. PAR64 is valid one clock after the initial address phase when
req64n
is
asserted and the DAC command is indicated on
c_ben[7:4]
. It is also valid the
clock cycle after the second address phase of a DAC command when
req64n
is
asserted.
c_ben[7:4]
I/O
req64n
I/O
ack64n
I/O
par64
I/O
Hot Swap Function Pins
enumn
O
Active-low open drain signal that notifies the system host that the card has been
freshly inserted or is about to be extracted. The system host can then either install
(for insertion) or quiesce (for extraction) the card’s driver to adjust for the change in
system configuration.
Active-low open-drain signal that drives a blue LED, indicating that removal of the
card is permitted. This signal is asserted low whenever the LED ON/OFF (LOO) bit
in the hot swap control and status register (HSSCR) is asserted high.
Active-high signal that indicates that the card’s ejector handle is unseated. This sig-
nals that the operator has freshly inserted the card, or will extract the card when the
blue LED illuminates. If not used, tie high or low.
PCI Bus Signaling Environment Voltage.
This input indicates to the PCI core the
signaling environment being employed on the PCI bus. The input is tied to the
appropriate voltage supply (either 5.0 V or 3.3 V).
ledn
O
ejectsw
I
vio
I
相關(guān)PDF資料
PDF描述
OR3TP12-6BA256 Single 2.3V 10 MHz OP w/ CS, I temp, -40C to +85C, 8-TSSOP, T/R
OR3TP12-6BA256I Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, TUBE
OR3TP12-6BA352 Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
OR3TP12-6BA352I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
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