- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383723 > OR3LP26B Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface PDF資料下載
參數(shù)資料
| 型號(hào)： | OR3LP26B |
| 英文描述： | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口 |
| 文件頁數(shù)： | 126/184頁 |
| 文件大?。?/td> | 5590K |
| 代理商： | OR3LP26B |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁當(dāng)前第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁
126
LLucent Technologies Inc.
ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
FPSC Configuration
The OR3LP26B FPSC provides the designer many
configuration options. In addition to all the configuration
options provided in the standard Series 3 architecture
(except Master parallel mode) including configuration
via the microprocessor and boundary-scan (JTAG)
interfaces, the OR3LP26B PCI FPSC also allows con-
figuration via the PCI interface. With this capability,
many configuration schemes can be implemented. For
example, a generic FPSC configuration can be loaded
via a serial configuration PROM and updated via the
PCI bus or the microprocessor interface. The FPSC
can also be reprogrammed in the field, or the configu-
ration can be dynamically modified to perform different
tasks.
When the FPSC is configured via the PCI interface,
there is a priority issue that must be resolved. The Sub-
system vendor ID and subsystem ID that reside at
2Ch—2Fh in the PCI configuration space can be
assigned during FPGA configuration, but these same
pieces of information may be needed by system soft-
ware to determine which FPSC configuration bit stream
to use for each FPSC when two or more FPSCs reside
on one PCI bus. For this reason, the OR3LP26B FPSC
is designed to allow for two different configuration
schemes.
The first option is more flexible; in this scheme, the
FPSC is first configured without employing the PCI
interface (e.g., via serial PROM). The access to the
FPSC's configuration registers via the PCI interface
occurs after this first configuration completes, so that
when the subsystem vendor ID and subsystem ID are
finally read, they properly and uniquely identify the card
on which the FPSC resides. This initial configuration bit
stream is only required to provide correct subsystem
vendor ID and subsystem ID values for system soft-
ware use, but it may in addition be the first version of
the FPSC's application code. The PCI system software
is then able to invoke the proper procedures that will
reconfigure the FPSC using the desired version of the
configuration bit stream.
The disadvantage of the first option is that it requires
that the FPSC be preconfigured prior to receiving the
working bit stream via the PCI interface. In a propri-
etary system, however, a second option may be
employed if the configuring software may already know
which bit stream to use to configure the FPSC. The
system software can simply locate the OR3LP26B by
reading the vendor ID and device ID, and then proceed
directly to FPSC configuration via the PCI bus. This
feature takes advantage of the fact that the PCI inter-
face is functional even before the FPSC has been con-
figured.
Configuration via PCI Bus
The OR3LP26B is configured using locations 40 hex
through 47 hex. These registers are dedicated to the
FPSC configuration and readback functions, as
detailed in Tables 36 and 37. The FPGA configuration
control-status register (FCCSR) is a 16-bit register at
address 40 hex—41 hex, and the FPGA configuration
data register (FCDR) is a 32-bit register at address
44 hex—47 hex.
The following is an example sequence which config-
ures the FPSC via the PCI interface:
1. Read the vendor ID and device ID registers. If the
vendor ID is 11C1 hex, the vendor, or chip manufac-
turer, is Lucent. If, in addition, the device ID is
5401 hex, the device is a Lucent OR3LP26B PCI
FPSC; go to step 2.
2. At this point, the configuration software may do one
of two things. If this is a proprietary system and the
configuration software already knows how to config-
ure any Lucent OR3LP26B, the software may skip
the next two steps, and the FPSC does not need to
be preconfigured. If this is a standard system, the
configuration software must perform the next two
steps to uniquely identify the application that is uti-
lizing the OR3LP26B.
3. Read the FCCSR [1] until Done goes active-high,
signaling that the FPSC preconfiguration operation
has completed, typically via a serial configuration
PROM.
4. Read the class code, revision ID, subsystem vendor
ID, and subsystem ID registers. This information is
programmed into the FPSC by the preconfiguration
step. This information is used by the configuration
software to locate the correct FPSC configuration
bit stream and driver for the FPSC's application,
and is provided by the manufacturer of the adapter
card containing the FPSC.
5. Read the FCCSR until bit 0 goes high. If communi-
cation with the FPSC is underway via the boundary-
scan hardware, this signal will remain inactive-low
until it completes.
6. Write to the FCCSR three times, first with PrgmN
high, then low, then high.
7. Write to the FCCSR with ConfigFPGA high. This will
initiate an FPSC configuration session via the PCI
interface.
8. Wait for the RAM initialization to complete by moni-
toring FCCSR [2]. Wait for 1.5 ms, and then send
one word of all ones. If
InitN
is high, continue with
real data; otherwise, repeat or declare the problem.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3TP12-6BA256 | Single 2.3V 10 MHz OP w/ CS, I temp, -40C to +85C, 8-TSSOP, T/R |
| OR3TP12-6BA256I | Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, TUBE |
| OR3TP12-6BA352 | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE |
| OR3TP12-6BA352I | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE |
| OR3TP12-6PS240 | Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3LP26BBA352-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3LP26BBM680-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T125 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-4BC432I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T125-4BC600I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。