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參數(shù)資料
| 型號： | OR3LP26B |
| 英文描述： | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）嵌入式主/目標PCI接口 |
| 文件頁數(shù)： | 50/184頁 |
| 文件大?。?/td> | 5590K |
| 代理商： | OR3LP26B |
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50
LLucent Technologies Inc.
ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
PCI Bus Core Detailed Description Dual
Port
(continued)
Nondelayed Transactions
Target memory and I/O write operations may work in a
nondelayed transaction mode. Once the PCI core Tar-
get determines that it is the intended recipient, it
asserts
devseln
and
trdyn
and begins loading data
into the Target write FIFO. After the core accepts the
data element that fills the FIFO, the next data element
will cause a disconnect without data. The operation is
then complete on the PCI bus; even if the FPGA par-
tially empties the Target write FIFO, no Target write
transaction, even a continuation of the previous burst,
will be accepted until the FIFO is emptied. The next
Target write operation will be considered a new trans-
action.
Delayed Transactions
Target I/O write operations may also be handled as
delayed transactions by asserting
deltrn
. The signal
deltrn
was designed to be a static signal. This signal
should be tied off high or low depending upon whether
the FPGA application wishes to run delayed transac-
tions. When asserting
deltrn
low, the PCI core will exe-
cute delayed transactions for I/O writes as well as all
target reads. In delayed transaction mode, the opera-
tion is not accepted on the first request. Instead, on the
first request, the PCI core records the command,
address, and first data word (32 or 64 bits) along with
its byte enables (4 or 8 bits). The first command and
address are put in the Target address FIFO, and the
data word and byte enables are put in the Target write
FIFO. The request is terminated in a retry, and the
FPGA application is informed as usual that a Target
request is pending via the assertion of
treqn
. Masters
are required to repeat requests terminated in retry until
data is moved (see PCI Specification section
3.3.3.2.2). The transaction status at this time is DWR
(delayed write request—see PCI Specification section
3.3.3.3.6), and subsequent requests will be terminated
in retry. When the FPGA application reads the FIFO
and empties it, the transaction status changes to DWC
(delayed write completion), and the next Target I/O
write that matches the stored command, address, data,
and byte enables will be accepted with a disconnect
with data, completing the transaction and clearing the
Target address and Target write FIFOs. Internal to the
ASIC, there is also a 15-bit time-out timer (known as
the discard timer). During a delayed I/O write transac-
tion, this counter will begin counting. If the same mas-
ter does not come back within 2
15
– 1
pciclk
's to
complete the write, this timer will expire, resetting the
target state machines and setting a user side signal
(
disctimerexp
= 1). From this point forward, any mas-
ter performing a write (including the original master
coming back to complete the transfer) will be treated as
a new transaction. If monitoring this signal, keep in
mind that
disctimerexp
is synchronous to
pciclk
and
asserts high for one clock period.
Termination
Nondelayed write transaction completion occurs when
the last item remaining in the Target write FIFO has
been read by the FPGA application (although the
actual PCI bus transaction may have completed much
earlier). Delayed write transaction completion occurs
when the I/O write results in a disconnect with data.
The PCI core signals end of transaction to the FPGA
application by deasserting
treqn
.
Reset
The FPGA application can apply the PCI core’s reset
signal
tfifoclrn
to place the core’s target logic in a
known state. Normally, the clear signal will not be used
unless a severe problem has occurred in the data flow.
The
tfifoclrn
signal is synchronous with
fclk
and must
be asserted for a minimum of three clock periods. Dur-
ing reset, the
t_ready
signal will go low. After the reset
signal is deasserted high,
t_ready
will continue to be
low for 8—10 clock periods. The FPGA application
should not continue normal operation until
t_ready
is
asserted high.
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