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參數(shù)資料
| 型號： | OR3LP26B |
| 英文描述： | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）嵌入式主/目標PCI接口 |
| 文件頁數(shù)： | 19/184頁 |
| 文件大?。?/td> | 5590K |
| 代理商： | OR3LP26B |
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Lucent Technologies Inc.
Lucent Technologies Inc.
19
Data Sheet
March 2000
ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description
(continued)
Table 7. PCI Bus Pin Descriptions
(continued)
Symbol
I/O
Description
Interface Control Pins
framen
I/O
Cycle Frame.
An active-low signal driven by the current Master to indicate the
beginning and duration of an access. The signal framen is asserted to indicate a
bus transaction is beginning. While
framen
is asserted, data transfers continue.
When
framen
is deasserted, the transaction is in the final phase or has completed.
Initiator Ready.
An active-low signal indicating the bus Master’s ability to complete
the current data phase of the transaction. The signal
irdyn
is used in conjunction
with
trdyn
. A data phase is completed on any clock cycle during which both
irdyn
and
trdyn
are asserted. During a write,
irdyn
indicates that valid data is present on
ad[31:0]
. During a read, it indicates the Master is prepared to accept data. Wait
cycles are inserted until both
irdyn
and
trdyn
are asserted together.
Target Ready.
An active-low signal asserted to indicate the readiness of the Tar-
get’s agent to complete the current data phase of the transaction. The signal
trdyn
is used in conjunction with
irdyn
. A data phase is completed on any clock where
both
trdyn
and
irdyn
are sampled active. During reads,
trdyn
indicates that valid
data is present on
ad[31:0]
lines. During write cycles,
trdyn
indicates that the Tar-
get is prepared to accept data.
STOPn.
Indicates that the current Target is requesting the Master to stop the cur-
rent transaction.
Initialization Device Select.
Used as a chip select during PCI configuration read
and write transactions. Generally, the user ties
idsel
to one of the upper 24 address
lines,
ad[31:8]
.
Device Select.
An active-low input indicating that a device on the bus has been
selected. As an output, it indicates that the driving device has decoded its address
as the Target of the current access.
Arbitration Pins (for Bus Master Only)
reqn
O
Request.
An active-low signal that indicates to the arbiter that the asserting agent
desires use of the bus. In the OR3LP26B, this signal is asserted when the
OR3LP26B Master controller needs access to the PCI bus.
gntn
I
Grant.
An active-low signal that indicates to the OR3LP26B that access to the PCI
bus has been granted.
Error Reporting Pins
perrn
I/O
Parity Error.
An active-low signal for the reporting of data parity errors during all
PCI transactions except a special cycle. The
perrn
pin is a sustained 3-state signal
and must be driven active by the agent receiving data two clocks following the data
when a data parity error is detected. The minimum duration of
perrn
is one clock for
each data phase that a data parity error is detected. If sequential data phases each
have a data parity error, the
perrn
signal will be asserted for more than a single
clock.
perrn
is driven high for one clock before being 3-stated. The signal
perrn
is
not asserted until it has claimed the access by asserting
devseln
and completed a
data phase.
irdyn
I/O
trdyn
I/O
stopn
I/O
idsel
I
devseln
I/O
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相關代理商/技術參數(shù) |
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| OR3LP26BBA352-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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| OR3T125-4BC432I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T125-4BC600I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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