參數(shù)資料
型號(hào)： OR3LP26B
英文描述： Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
中文描述： 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口
文件頁(yè)數(shù)： 53/184頁(yè)
文件大?。?/td> 5590K
代理商： OR3LP26B
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Lucent Technologies Inc.
Lucent Technologies Inc.
53
Data Sheet
March 2000
ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description
Dual Port
(continued)
Target Write I/O, Delayed Transaction
Figure 11 (PCI bus) and Figure 13 (FPGA bus) show the timing for a Target I/O write operation that is handled as a
delayed transaction; that is, the operation completes on the local (FPGA) bus before completing on the PCI bus.
The FPGA application indicates its desire to do this by asserting signal
deltrn
. In Figure 11, three transactions are
shown: the first is the initial write that latches the command, address, data, and byte enables in the PCI core. The
core's Target logic then issues a retry, obligating the remote Master to continue to issue that identical request until
data is moved. Meanwhile, the information is relayed to the FPGA interface via the address and data FIFOs, trig-
gering the FPGA interface exchange discussed below and shown in Figure 13. All subsequent read or write
requests to memory, I/O, or configuration space will result in retries, as shown in the second transaction of Figure
11. The third transaction is the final transaction that completes the transfer of data. Although the data was actually
latched and forwarded to the FPGA from the first transaction, it is not until the FPGA acknowledges that it has
received the data, by emptying the Target write FIFO, that the PCI core acknowledges to the remote Master that it
has received the data by performing a disconnect with data. The timing on this third transaction is identical to the
timing of the first except that
trdyn
accompanies
stopn
to indicate the disconnect with data.
The timing on the FPGA interface (Figure 13) shows that the first indication to the FPGA application that a new
operation has begun is the assertion of target request (
treqn
), together with the new command on bus
datatofpga
. The FPGA application responds by asserting target address enable (
taenn
) and accepting the com-
mand and subsequent address on bus datatofpga. This is followed by deassertion of
taenn
, assertion of Target
write data enable (
twdataenn
), and the receiving of the data on bus
datatofpga
. Although only 32 bits of data are
being transferred, the FPGA application must accept 64 bits of data (two clock cycles) because the FIFOs are
operating in 64-bit mode.
5-7372(F).a
Figure 11. Target I/O Write, Delayed (PCI Bus, 64-Bit)
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
Ta6
Tb0
Tb1
Tb2
Tb3
Tb4
Tb5
Tb6
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
X
ADRS
DATA
X
X
ADRS
DATA
X
X
ADRS
DATA
X
X
CMD
BEs
X
X
CMD
BEs
X
X
CMD
BEs
X
clk
framen
ad[31:0]
c/be[3:0]n
irdyn
devseln
trdyn
stopn
TRANSACTION #1: ADDRESS, BYTE ENABLES,
COMMAND, AND WRITE DATA LATCHED AS A
DELAYED WRITE REQUEST.
TRANSACTION #2: DISCONNECTED W/O DATA
BECAUSE WRITE COMPLETION NOT RECEIVED.
TRANSACTION #3: DISCONNECTED WITH DATA
BECAUSE WRITE COMPLETION RECEIVED.
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