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參數(shù)資料
| 型號(hào)： | OR3LP26B |
| 英文描述： | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
| 中文描述： | 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口 |
| 文件頁數(shù)： | 7/184頁 |
| 文件大小： | 5590K |
| 代理商： | OR3LP26B |
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Lucent Technologies Inc.
Lucent Technologies Inc.
7
Data Sheet
March 2000
ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
Description
What Is an FPSC
FPSCs, or field-programmable system chips, are
devices that combine field-programmable logic with
ASIC or mask-programmed logic on a single device.
FPSCs provide the time to market and flexibility of
FPGAs, the design effort savings of using soft intellec-
tual property (IP) cores, and the speed, design density,
and economy of ASICs.
FPSC Overview
Lucent’s Series 3+ FPSCs are created from Series 3
ORCA FPGAs. To create a Series 3+ FPSC, several
rows of programmable logic cells (see FPGA Logic
Overview section for FPGA logic details) are removed
from a Series 3 ORCAFPGA, and the area is replaced
with an embedded logic core. Other than replacing
some FPGA gates with ASIC gates, at greater than
10:1 efficiency, none of the FPGA functionality is
changed—all of the Series 3 FPGA capability is
retained: MPI, PCMs, boundary scan, etc. The rows of
programmable logic are replaced at the bottom of the
device, allowing pins on the bottom and sides of the
replaced rows to be used as I/O pins for the embedded
core. The remainder of the device pins retain their
FPGA functionality as do special function FPGA pins
within the embedded core area.
The embedded cores can take many forms and gener-
ally come from Lucent Technologies ASIC libraries.
Future offerings will allow customers to supply their
own core functions for the creation of custom FPSCs.
FPSC Gate Counting
The total gate count for an FPSC is the sum of its
embedded core (standard-cell/ASIC gates) and its
FPGA gates. Because FPGA gates are generally
expressed as a usable range with a nominal value, the
total FPSC gate count is sometimes expressed in the
same manner. Standard-cell/ASIC gates are, however,
10 to 25 times more silicon area efficient than FPGA
gates. Therefore, an FPSC with an embedded function
is gate equivalent to an FPGA with a much larger gate
count.
FPGA/Embedded Core Interface
The interface between the FPGA logic and the embed-
ded core is designed to look like FPGA I/Os from the
FPGA side, simplifying interface signal routing and pro-
viding a unified approach with general FPGA design.
Effectively, the FPGA is designed as if signals were
going off of the device to the embedded core, but the
on-chip interface is much faster than going off-chip and
requires less power. All of the delays for the interface
are precharacterized and accounted for in the ORCA
Foundry Development System.
Clock spines also can pass across the FPGA/embed-
ded core boundary. This allows for fast, low-skew clock-
ing between the FPGA and the embedded core. Many
of the special signals from the FPGA, such as DONE
and global set/reset, are also available to the embed-
ded core, making it possible to fully integrate the
embedded core with the FPGA as a system.
For even greater system flexibility, FPGA configuration
RAMs are available for use by the embedded core. This
allows for user-programmable options in the embedded
core, in turn allowing for greater flexibility. Multiple
embedded core configurations may be designed into a
single device with user-programmable control over
which configurations are implemented, as well as the
capability to change core functionality simply by recon-
figuring the device.
ORCA
Foundry
Development System
The ORCAFoundry Development System is used to
process a design from a netlist to a configured FPSC.
This system is used to map a design onto the ORCA
architecture and then place and route it using ORCA
Foundry’s timing-driven tools. The development system
also includes interfaces to, and libraries for, other popu-
lar CAE tools for design entry, synthesis, simulation,
and timing analysis.
The ORCA Foundry Development System interfaces to
front-end design entry tools and provides the tools to
produce a configured FPSC. In the design flow, the
user defines the functionality of the FPGA portion of
the FPSC and embedded core settings at two points in
the design flow: at design entry and at the bit stream
generation stage.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3TP12-6BA256 | Single 2.3V 10 MHz OP w/ CS, I temp, -40C to +85C, 8-TSSOP, T/R |
| OR3TP12-6BA256I | Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, TUBE |
| OR3TP12-6BA352 | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE |
| OR3TP12-6BA352I | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE |
| OR3TP12-6PS240 | Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3LP26BBA352-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3LP26BBM680-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 FPSC PCI INTERFACE RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3T125 | 制造商:AGERE 制造商全稱:AGERE 功能描述:3C and 3T Field-Programmable Gate Arrays |
| OR3T125-4BC432I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| OR3T125-4BC600I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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