參數(shù)資料
型號(hào)： OR3LP26B
英文描述： Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
中文描述： 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）嵌入式主/目標(biāo)PCI接口
文件頁(yè)數(shù)： 70/184頁(yè)
文件大?。?/td> 5590K
代理商： OR3LP26B
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ORCAOR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
70
L Lucent Technologies Inc.
PCI Bus Core Detailed Description Quad Port
Pages 70—122 will refer to the quad-port mode of the OR3LP26B device. For dual-port mode, please refer to
pages 21—69.
Embedded Core/FPGA Interface Signal Descriptions
In Table 23, an input refers to a signal flowing into the FPGA logic (out of the embedded core) and an output refers
to a signal flowing out of the FPGA logic (into the embedded core).
Table 23. Embedded Core/FPGA Interface Signals
Symbol
I/O
Description
Master Data FIFO Signals
mwdata[35:0]
O
Main data bus into the master write FIFO. Refer to Table 25 on page 79 for bus
usage and bit descriptions.
These signals must be synchronous to
fclk
.
Main data bus out of the master read FIFO. Refer to Table 25 on page 79 for bus
usage and bit descriptions.
These signals are synchronous to
fclk
.
mrdata[35:0]
I
Master General Signals
fpga_mbusyn
O
FPGA Master Is Busy.
This signal is used in modes currently not implemented in
the core. Tie off this signal to a 1.
FPGA Master Cycle Aborted by PCI Target.
The PCI Master controller in the PCI
core asserts this active-high as an indication that the current cycle to the PCI bus
has been aborted. This signal is synchronous to
fclk
.
mcfgshiftenn
is an active-low signal that determines the data that is output by the
PCI core onto signal
pci_mcfg_stat
:
mcfgshiftenn
= 1:
pci_mcfg_stat
= wired-OR of all bits below, after being
masked by FPGA configuration RAM bits;
mcfgshiftenn
= 0:
pci_mcfg_stat
= each bit below, one at a time on succes-
sive
pciclk
rising edges (unmasked), reset when
mcfgshiftenn
= 1;
Status bits:
Data parity error detected, Target abort received, and
Master abort received.
Both signals are synchronous to
fclk
.
Master FIFO Address and Command Register Control Signals
Symbol
I/O
maenn
O
Master Command/Address/Burst Length Enable.
This is an active-low signal
and is used to enable registering commands, burst length, and start address into
the Master address register of the PCI core. On each rising edge of the clock that
this signal is sampled low, command, burst length, and address will be registered.
This signal must be synchronous to
fclk
.
ma_fulln
I
Master Address Register Full Flag.
This active-low signal indicates that the Mas-
ter address register is full and no more addresses can be registered.
This signal is synchronous to
fclk
.
mstatecntr[2:0]
I
Internal State Counter.
Used for Master reads and writes. Details of the Master
state machine operation can be found in tables at the end of each operation sec-
tion.
This signal is synchronous to
fclk
.
mfifoclrn
O
Master FIFO Clear.
This active-low signal is asserted by the FPGA Master to clear
all Master FIFOs.
This signal must be synchronous to
fclk
.
fpga_msyserror
I
mcfgshiftenn
pci_mcfg_stat
O
I
Description
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