- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > Am79C965A (Advanced Micro Devices, Inc.) PCnet?-32 Single-Chip 32-Bit Ethernet Controller PDF資料下載
參數(shù)資料
| 型號： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 98/228頁 |
| 文件大?。?/td> | 1681K |
| 代理商： | AM79C965A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁當(dāng)前第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁
98
Am79C965A
Link Test Function
The link test function is implemented as specified by
10BASE-T standard. During periods of transmit pair in-
activity,
’
Link beat pulses
’
will be periodically sent over
the twisted pair medium to constantly monitor medium
integrity.
When the link test function is enabled (DLNKTST bit in
CSR15 is cleared), the absence of link beat pulses and
receive data on the RXD± pair will cause the T-MAU to
go into a link fail state. In the link fail state, data
transmission, data reception, data loopback and the
collision detection functions are disabled, and remain
disabled until valid data or >5 consecutive link pulses
appear on the RXD± pair. During link fail, the Link
Status signal is inactive. When the link is identified as
functional, the Link Status signal is asserted. The
LNKST pin displays the Link Status signal by default.
Transmission attempts during Link Fail state will pro-
duce no network activity and will produce LCAR and
CERR error indications.
In order to inter-operate with systems which do not im-
plement Link Test, this function can be disabled by set-
ting the DLNKTST bit in CSR15. With link test disabled,
the data driver, receiver and loopback functions as well
as collision detection remain enabled regardless of the
presence or absence of data or link pulses on the
RXD± pair. Link Test pulses continue to be sent
regardless of the state of the DLNKTST bit.
Polarity Detection and Reversal
The T-MAU receive function includes the ability to invert
the polarity of the signals appearing at the RXD± pair if
the polarity of the received signal is reversed (such as
in the case of a wiring error). This feature allows data
frames received from a reverse wired RXD± input pair
to be corrected in the T-MAU prior to transfer to the
MENDEC. The polarity detection function is activated
following H_RESET or Link Fail, and will reverse the
receive polarity based on both the polarity of any
previous link beat pulses and the polarity of
subsequent frames with a valid End Transmit Delimiter
(ETD).
When in the Link Fail state, the T-MAU will recognize
link beat pulses of either positive or negative polarity.
Exit from the Link Fail state is made due to the
reception of 5
–
6 consecutive link beat pulses of
identical polarity. On entry to the Link Pass state, the
polarity of the last 5 link beat pulses is used to
determine the initial receive polarity configuration and
the receiver is reconfigured to subsequently recognize
only link beat pulses of the previously recognized
polarity.
Positive link beat pulses are defined as received signal
with a positive amplitude greater than 585 mV (LRT =
HIGH) with a pulse width of 60 ns
–
200 ns. This positive
excursion may be followed by a negative excursion.
This definition is consistent with the expected received
signal at a correctly wired receiver, when a link beat
pulse which fits the template of Figure 14-12 of the
10BASE-T Standard is generated at a transmitter and
passed through 100 m of twisted pair cable.
Negative link beat pulses are defined as received
signals with a negative amplitude greater than 585 mV
with a pulse width of 60 ns
–
200 ns. This negative
excursion may be followed by a positive excursion. This
definition is consistent with the expected received
signal at a reverse wired receiver, when a link beat
pulse which fits the template of Figure 14-12 in the
10BASE-T Standard is generated at a transmitter and
passed through 100 m of twisted pair cable.
The polarity detection/correction algorithm will remain
“
armed
”
until two consecutive frames with valid ETD of
identical polarity are detected. When
“
armed
”
, the re-
ceiver is capable of changing the initial or previous po-
larity configuration based on the ETD polarity.
On receipt of the first frame with valid ETD following
H_RESET or link fail, the T-MAU will utilize the inferred
polarity information to configure its RXD± input, regard-
less of its previous state. On receipt of a second frame
with a valid ETD with correct polarity, the detection/cor-
rection algorithm will
“
lock-in
”
the received polarity. If
the second (or subsequent) frame is not detected as
confirming the previous polarity decision, the most
recently detected ETD polarity will be used as the
default. Note that frames with invalid ETD have no
effect on updating the previous polarity decision. Once
two consecutive frames with valid ETD have been
received, the T-MAU will disable the detection/
correction algorithm until either a Link Fail condition
occurs or H_RESET is activated.
During polarity reversal, an internal POL signal will be
active. During normal polarity conditions, this internal
POL signal is inactive. The state of this signal can be
read by software and/or displayed by LED when en-
abled by the LED control bits in the Bus Configuration
Registers (BCR4
–
BCR7).
Twisted Pair Interface Status
Three signals (XMT, RCV and COL) indicate whether
the T-MAU is transmitting, receiving, or in a collision
state with both functions active simultaneously. These
signals are internal signals and the behavior of the LED
outputs depends on how the LED Output circuiting is
programmed.
The T-MAU will power up in the Link Fail state and the
normal algorithm will apply to allow it to enter the Link
Pass state. In the Link Pass state, transmit or receive
activity will be indicated by assertion of RCV signal go-
ing active. If T-MAU is selected using the PORTSEL
bits in CSR15, then when moving from AUI to T-MAU
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C970AKCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970A | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AVCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970 | PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C965AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
| AM79C970 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C970A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。