
Am79C965A
127
5
RXON
Receive On indicates that the
Receive function is enabled. RXON
is set if DRX (CSR15[0]) =
“
0
”
after
the START bit is set. If INIT and
START are set together, RXON will
not be set until after the initialization
block has been read in.
RXON is read only. RXON is cleared
by H_RESET or S_RESET or
setting the STOP bit.
4
TXON Transmit On indicates that the
Transmit function is enabled. TXON
is set if DTX (CSR15[1]) =
“
0
”
after
the START bit is set. If INIT and
START are set together, TXON will
not be set until
after the initialization
block has
been read in. TXON is read
only. TXON is cleared by H_RESET
or S_RESET or setting the STOP
bit.
3
TDMD Transmit Demand, when set, causes
the Buffer Management Unit to
access the Transmit Descriptor Ring
without waiting for the poll-time
counter to elapse. If TXON is not
enabled, TDMD bit will be reset and
no Transmit Descriptor Ring access
will occur.
TDMD is required to be set if the
DPOLL bit in CSR4 is set. Setting
TDMD while DPOLL = 0 merely
hastens the PCnet-32 controller
’
s
response to a Transmit Descriptor
Ring Entry.
TDMD is set by writing a
“
1
”
. Writing
a
“
0
”
has no effect. TDMD will be
cleared by the Buffer Management
Unit when it fetches a Transmit
Descriptor. TDMD is cleared by
H_RESET or S_RESET or setting
the STOP bit.
2
STOP
STOP assertion disables the chip
from all DMA activity. The chip
remains inactive until either STRT or
INIT are set. If STOP, STRT and INIT
are all set together, STOP will
override STRT and INIT.
STOP is set by writing a
“
1
”
or by
H_RESET or S_RESET. Writing a
“
0
”
has no effect. STOP is cleared by
setting either STRT or INIT.
1
STRT
STRT assertion enables PCnet-32
controller to send and receive
frames, and perform buffer
management operations. Setting
STRT clears the STOP bit. If STRT
and INIT are set together, PCnet-32
controller initialization will be
performed first.
STRT is set by writing a
“
1
”
. Writing
a
“
0
”
has no effect. STRT is cleared
by H_RESET or S_RESET or by
setting the STOP bit.
0
INIT
INIT assertion enables PCnet-32
controller to begin the initialization
procedure which reads in the
initialization block from memory.
Setting INIT clears the STOP bit. If
STRT and INIT are set together,
PCnet-32 controller initialization will
be performed first.
INIT is not cleared when the
initialization sequence has
completed.
INIT is set by writing a
“
1
”
. Writing a
“
0
”
has
no effect. INIT is cleared by
H_RESET or S_RESET or by
setting the STOP bit.
CSR1: IADR[15:0]
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
IADR[15:0] Lower 16 bits of the address of
the Initialization Block.
Regardless
SSIZE32(BCR20/CSR58, bit 8)
IADR[1:0] must be zero.
of
the
value
of
This register is aliased with CSR16.
Read/Write accessible only when
the STOP bit in CSR0 is set.
Unaffected by H_RESET or
S_RESET or by setting the STOP
bit.
CSR2: IADR[31:16]
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-8 IADR[31:24] If SSIZE32 is set (BCR20[8]), then
the IADR[31:24] bits will be used
strictly as the upper 8 bits of the
initialization block address.
However, if SSIZE32 is reset, then
the IADR[31:24] bits will be used to
generate the upper 8 bits of all bus