參數(shù)資料
型號： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁數(shù)： 103/228頁
文件大?。?/td> 1681K
代理商： AM79C965A
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Am79C965A
103
Table 31. GPSI Pin Configurations
Note that the XTAL1 input must always be driven with a
clock source, even if GPSI mode is to be used. It is not
necessary for the XTAL1 clock to meet the normal
frequency and stability requirements in this case. Any
frequency between 8 MHz and 20 MHz is acceptable.
However, voltage drive requirements do not change.
When GPSI mode is used, XTAL1 must be driven for
several reasons:
1. The default pin RESET configuration for the
PCnet-32 controller is
“
AUI port selected,
”
and until
GPSI mode is selected, the XTAL1 clock is needed
for some internal operations (namely, RESET).
2. The XTAL1 clock drives the EEPROM read opera-
tion, regardless of the network mode selected.
3. The XTAL1 clock determines the length of a Reset
Register read operation, regardless of the network
mode selected (due to the internal RESET caused
by the read).
Note that if a clock slower than 20 MHz is provided at
the XTAL1 input, the time needed for EEPROM read
and Reset Register Read operations will increase.
Power Savings Modes
The PCnet-32 controller supports two hardware power
savings modes. Both are entered by driving the SLEEP
pin LOW.
In
coma
mode, the PCnet-32 controller will go into a
deep sleep with no means to use the network to auto-
matically wake itself up. Coma mode is enabled when
the AWAKE bit in BCR2 is reset. Coma mode is the de-
fault power down mode. When coma mode is invoked,
the T-MAU circuitry will go into power down mode. The
system bus interface will be floated and inactive during
coma mode. LDEV and the selected interrupt pin will
be driven to inactive levels. While in coma mode, if the
PCnet-32 controller is configured for a daisy chain
(HOLDI and HLDAO or LREQI and LGNTO signals
have been selected with the JTAGSEL pin), then the
daisy chain signal LREQI/HOLDI will be passed
directly to LREQ/HOLD and the system arbitration
signal LGNT/ HLDA will be passed directly to the daisy-
chain signal LGNTO/HLDAO.
In
snooze
mode, enabled by setting the AWAKE bit in
BCR2 and driving the SLEEP pin LOW, the T-MAU re-
ceive circuitry will remain enabled even while the
SLEEP pin is driven LOW. The LNKST output will also
continue to function, indicating a good 10BASE-T link if
there are link beat pulses or valid frames present. This
LNKST pin can be used to drive an LED and/or external
hardware that directly controls the SLEEP pin of the
PCnet-32 controller. This configuration effectively
wakes the system when there is any activity on the
10BASE-T link. Auto wake mode can be used only if
the T-MAU is the selected network port. Link beat
pulses are not transmitted during Auto-wake mode.
The system bus interface will be floated and inactive
during snooze mode. LDEV and the selected interrupt
pin will be driven to inactive levels. While in snooze
mode, if the PCnet-32 controller is configured for a
daisy chain (HOLDI and HLDAO or LREQI and LGNTO
signals have been selected with the JTAGSEL pin),
then the daisy chain signal LREQI/HOLDI will be
passed directly to LREQ/HOLD and the system
arbitration signal LGNT/HLDA will be passed directly to
the daisy-chain signal LGNTO/HLDAO.
If the HOLD output is active when the SLEEP pin is as-
serted, then the PCnet-32 controller will wait until the
HLDA input is asserted. Then the PCnet-32 controller
will de-assert the HOLD pin and finally, it will internally
enter either the coma or snooze sleep mode.
Before the sleep mode is invoked, the PCnet-32
controller will perform an internal S_RESET. This
S_RESET operation will not affect the values of the
BCR registers.
The SLEEP pin should not be asserted during power
supply ramp-up. If it is desired that SLEEP be asserted
at power up time, then the system must delay the
assertion of SLEEP until three BCLK cycles after the
completion of a valid pin RESET operation.
GPSI Function
GPSI
I/O
Type
LANCE
GPSI Pin
ILACC
GPSI Pin
PCnet-32/
PCnet-ISA
GPSI Pin
PCnet-32
Pin
Number
PCnet-32
Normal
Pin Function
Transmit Data
O
TX
TXD
TXDAT
132
A31
Transmit Enable
O
TENA
RTS
TXEN
133
A30
Transmit Clock
I
TCLK
TXC
STDCLK
134
A29
Collision
I
CLSN
CDT
CLSN
137
A28
Receive Clock
I
RCLK
RXC
SRDCLK
140
A26
Receive Data
I
RX
RXD
RXDAT
141
A25
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參數(shù)描述
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