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參數(shù)資料
| 型號： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 91/228頁 |
| 文件大?。?/td> | 1681K |
| 代理商： | AM79C965A |
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Am79C965A
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exceeds the length of the first buffer, and the PCnet-32
controller does not own the second buffer, ownership of
the current descriptor will be passed back to the
system by writing a zero to the OWN bit of RMD1 and
status will be written indicating buffer (BUFF=1) and
possibly overflow (OFLO=1) errors.
If the frame length exceeds the length of the first (cur-
rent) buffer, and the PCnet-32 controller does own the
second (next) buffer, ownership will be passed back to
the system by writing a zero to the OWN bit of RMD1
when the first buffer is full. Receive data transfers to the
second buffer may occur before the PCnet-32
controller proceeds to look ahead to the ownership of
the third buffer. Such action will depend upon the state
of the FIFO when the status has been updated on the
first descriptor. In any case, look-ahead will be
performed to the third buffer and the information
gathered will be stored in the chip, regardless of the
state of the ownership bit. As in the transmit flow, look-
ahead operations are performed only once.
This activity continues until the PCnet-32 controller rec-
ognizes the completion of the frame (the last byte of
this receive message has been removed from the
FIFO). The PCnet-32 controller will subsequently
update the current RDTE status with the end of frame
(ENP) indication set, write the message byte count
(MCNT) of the complete frame into RMD2 and
overwrite the
“
current
”
entries in the CSRs with the
“
next
”
entries.
Media Access Control
The Media Access Control engine incorporates the es-
sential protocol requirements for operation of a compli-
ant Ethernet/802.3 node, and provides the interface
between the FIFO subsystem and the Manchester
Encoder/ Decoder (MENDEC).
The MAC engine is fully compliant to Section 4 of ISO/
IEC 8802-3 (ANSI/IEEE Standard 1990 Second
edition) and ANSI/IEEE 802.3 (1985).
The MAC engine provides programmable enhanced
features designed to minimize host supervision, bus
utilization, and pre- or post-message processing.
These include the ability to disable retries after a
collision, dynamic FCS generation on a frame-by-frame
basis, and automatic pad field insertion and deletion to
enforce minimum frame size attributes and reduces
bus bandwidth use.
The two primary attributes of the MAC engine are:
I
Transmit and receive message data encapsulation.
—
Framing (frame boundary delimitation, frame
synchronization)
—
Addressing (source and destination address
handling)
—
Error detection (physical medium transmission
errors)
I
Media access management.
—
Medium allocation (collision avoidance)
—
Contention resolution (collision handling)
Transmit and Receive Message Data Encapsulation
The MAC engine provides minimum frame size
enforcement for transmit and receive frames. When
APAD_XMT = 1 (CSR4[11]), transmit messages will be
padded with sufficient bytes (containing 00h) to ensure
that the receiving station will observe an information
field (destination address, source address, length/type,
data and FCS) of 64 bytes. When ASTRP_RCV = 1
(CSR4[10]), the receiver will automatically strip pad
bytes from the received message by observing the
value in the length field, and stripping excess bytes if
this value is below the minimum data size (46 bytes).
Both features can be independently overridden to allow
illegally short (less than 64 bytes of frame data)
messages to be transmitted and/or received. Use of
this feature decreases bus usage because the pad
bytes are not transferred into or out of host memory.
Framing (Frame Boundary Delimitation, Frame
Synchronization)
The MAC engine will autonomously handle the con-
struction of the transmit frame. Once the Transmit FIFO
has been filled to the predetermined threshold (set by
XMTSP in CSR80), and providing access to the
channel is currently permitted, the MAC engine will
commence the 7-byte preamble sequence
(10101010b, where first bit transmitted is a 1). The
MAC engine will subsequently append the Start Frame
Delimiter (SFD) byte (10101011b) followed by the
serialized data from the Transmit FIFO. Once the data
has been completed, the MAC engine will append the
FCS (most significant bit first) which was computed on
the message (destination address, source address,
length field, data field, and pad (if applicable)).
Note that the user is responsible for the correct
ordering and content in each of the fields in the frame,
including the destination address, source address,
length/type and frame data.
The receive section of the MAC engine will detect an
incoming preamble sequence and lock to the encoded
clock. The internal MENDEC will decode the serial bit
stream and present this to the MAC engine. The MAC
will discard the first 8-bits of information before search-
ing for the SFD sequence. Once the SFD is detected,
all subsequent bits are treated as part of the frame. The
MAC engine will inspect the length field to ensure mini-
mum frame size, strip unnecessary pad characters (if
enabled), and pass the remaining bytes through the
Receive FIFO to the host. If pad stripping is performed,
the MAC engine will also strip the received FCS bytes,
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相關(guān)代理商/技術(shù)參數(shù) |
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