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參數(shù)資料
| 型號： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 63/228頁 |
| 文件大?。?/td> | 1681K |
| 代理商： | AM79C965A |
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Am79C965A
63
Linear Burst DMA Timing Diagram Explanatory
Note
Note that in all of the following timing diagrams for
linear burst operations, a LINBC[2:0] value of 001 has
been assumed. This translates to a linear burst length
of four transfers. When the linear burst size is four
transfers, then A[31:4] are stable within a single linear
burst sequence, while A[3:2] and BE3
–
BE0 will change
to reflect the address of the current transfer. Note that
for larger values of LINBC[2:0] which correspond to
longer linear burst lengths, the range of address pins
that is stable during each burst sequence is smaller.
For example, if LINBC[2:0] has the value of 010, then
the linear burst length is eight double word transfers or
32 bytes of data. With this value of LINBC, it takes five
address bits to track the changing addresses through
the burst. This means that only A[31:5] are stable
during each linear burst sequence, while A[4:2] and
BE3
–
BE0 will change to reflect the address of the
current transfer. For LINBC[2:0] = 100, only A[31:6] are
stable during each linear burst sequence, while A[5:2]
and BE3
–
BE0 will change to reflect the address of the
current transfer, and
so on. Table 22 summarizes this
information.
Table 22. Stable Address Lines During
Linear Burst
Values of LINBC not shown in the table are not allowed.
See the LINBC section of BCR18 for more details.
Since all of the timing diagrams assume a LINBC[2:0]
value of 001, then A[31:4] are shown to be stable within
each linear burst sequence, and A[3:2] and BE3
–
BE0
are shown as changing in order to reflect the address
of the current transfer.
Linear Burst DMA Address Alignment
Linear bursting may begin during a bus mastership pe-
riod which was initially performing only ordinary DMA
operations. (i.e. the value of BLAST is not restricted to
ZERO for an entire bus mastership period if ZERO was
the value of BLAST on the first access of a bus master-
ship period.) A change from non-linear bursting to
linear bursting will normally occur during linear burst
DMA address alignment operations.
If the PCnet-32 controller is programmed for LINEAR
burst mode (i.e. BREADE and/or BWRITE bits of
BCR18 are set to ONE), and the PCnet-32 controller
requests the bus, but the starting address of the first
transaction does not meet the conditions as specified
in the table above, then the PCnet-32 controller will
perform burst-cycle accesses (i.e. it will provide an
ADS for each transfer) until it arrives at an address that
does meet the conditions described in the table. At that
time, and without releasing the bus, the PCnet-32
controller will invoke the linear burst mode. The simple
external manifestation of this event is that the value of
the BLAST signal will change to de-asserted (driven
high) on the next T2 cycle, thereby indicating a
willingness of the PCnet-32 controller to perform linear
bursting. (Note that burst-cycle accesses are
performed with BLAST = 0.)
Figure 13 shows an example of a linear burst DMA
alignment operation being performed:
LINBC Value
Portion of Address Bus
Stable During Linear Burst
000
Linear Bursting Disabled
001
A[31:4]
010
A[31:5]
100
A[31:6]
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相關(guān)代理商/技術(shù)參數(shù) |
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