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參數(shù)資料
| 型號： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 70/228頁 |
| 文件大?。?/td> | 1681K |
| 代理商： | AM79C965A |
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70
Am79C965A
Length of Bus Mastership Period
The number of data transfer cycles within the total bus
mastership period is dependent on the programming of
the DMAPLUS option (CSR4, bit 14). The possibilities
are as follows:
If DMAPLUS = 0, a maximum of 16 transfers will be
performed by default. This default value may be
changed by writing to the burst register (CSR80). Note
that DMAPLUS = 0 merely sets a maximum value. The
minimum number of transfers in the burst will be
determined by all of the following variables: the settings
of the FIFO watermarks and the conditions of the
FIFOs, the value of the DMA Burst Cycle (CSR80), the
value of the DMA Bus Activity Timer (CSR82), and any
occurrence of preemption that takes place during the
burst.
If DMAPLUS = 1, linear bursting will continue until the
transmit FIFO is filled to its high threshold or the
receive FIFO is emptied to its low threshold, or until the
DMA Bus Activity Timer value (CSR82) has expired. A
bus preemption event is another cause of termination
of cycles. The FIFO thresholds are programmable (see
description of CSR80), as are the Burst Cycle and Bus
Activity Timer values. The exact number of total
transfer cycles in the case of DMAPLUS = 1 will be
dependent on the latency of the system bus to the
PCnet-32 controller
’
s mastership request and the
speed of bus operation, but will be limited by the value
in the Bus Activity Timer Register, the FIFO condition
and by preemption occurrences, if any.
The exact response of the PCnet-32 controller to any of
the conditions mentioned above can be complicated.
For detail of the response to any particular stimulus,
see each of the sections that describes PCnet-32
controller response.
Note that the number of transfer cycles between each
ADS assertion will always only be controlled by LINBC,
RDYRTN, BOFF, HLDA and FIFO conditions. The num-
ber of transfer cycles separating ADS assertions will
not be affected by DMAPLUS or by the values in the
Burst Cycle and Bus Activity Timer Register. However,
these factors can influence the number of transfers that
is performed during any given arbitration cycle.
Barring a time-out by the Burst Cycle or the Bus Activity
Timer Register, or a bus preemption by another
mastering device, the FIFO watermark settings and the
extent of Bus Acknowledge latency will be the major
factors in determining the number of accesses
performed during any given arbitration cycle. The
BRDY response time of the memory device will also
affect the number of transfers, since the speed of the
accesses will affect the state of the FIFO. (During
accesses, the FIFO may be filling or emptying on the
network end. For example, on a Receive operation, a
slower device will allow additional data to accumulate
inside of the FIFO. If the accesses are slow enough, a
complete double word may become available before
the end of the arbitration cycle and thereby increase
the number of transfers in that cycle.) The general rule
is that the longer the bus grant latency or the slower the
bus transfer operations or the slower the clock speed or
the higher the transmit watermark or the lower the
receive watermark or any combination thereof, will
produce longer total burst lengths.
If a bus preemption event occurs after the execution of
the first T2 cycle of the fourth from the last transfer
cycle within a linear burst DMA sequence, then the
PCnet-32 controller will complete the current linear
burst sequence and will execute a new linear burst
sequence before releasing the HOLD signal and
relinquishing the bus. If a bus preemption event occurs
before or concurrent with the execution of the first T2
cycle of the fourth from the last transfer cycle within a
linear burst DMA sequence, then the PCnet-32
controller will complete the current linear burst
sequence and then will release the HOLD signal and
will relinquish the bus. Within the context of this
explanation, a single transfer cycle refers to the
execution of a data transfer, regardless of the number
of clock cycles taken, i.e. wait states are included in this
definition of a transfer cycle. See Figure 18.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AM79C965AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
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| AM79C970A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
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