參數(shù)資料
型號(hào)： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁數(shù)： 160/228頁
文件大?。?/td> 1681K
代理商： AM79C965A
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160
Am79C965A
IOBASEL value to be updated.
Refer to the Software Relocatable
Mode section of this document for
more details.
A direct write access to the I/O Base
Address Lower register may be
performed.
IOBASEL
S_RESET or STOP.
is
not
affected
by
4-0
RES
Reserved locations. Written as
ZEROs, read as undefined.
BCR17: I/O Base Address Upper
Bit
Name
Description
Note that all bits in this register are
programmable through the
EEPROM PREAD operation and
software relocatable mode.
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
IOBASEU I/O Base Address Upper 16 bits.
These bits are used to determine
the location of the PCnet-32
controller in all of I/O space. They
function as bits 31 through 16 of the
I/O address of the PCnet-32
controller. The value of IOBASEU is
determined in either of two ways:
1. The IOBASEU value may be set
during the EEPROM read.
2. If no EEPROM exists, or if there is
an error detected in the EEPROM
data, then the PCnet-32 controller
will enter Software Relocatable
Mode, and a specific sequence of
write accesses to I/O address
378h will cause the IOBASEU
value to be updated. Refer to the
Software Relocatable Mode
section of this document for more
details.
A direct write access to the I/O Base
Address Upper register may be
performed.
IOBASEU
S_RESET or STOP.
is
not
affected
by
BCR18: Burst Size and Bus Control
Bit
Name
Description
Note that all bits in this register are
programmable through the
EEPROM PREAD operation.
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-11 CLL
Cache Line Length. These bits are
used to determine how often a
cache invalidation cycle needs to be
performed when Generate Cache
Invalidation Cycles has been
activated by setting the GCIC bit (bit
10 of BCR18) to a one. CLL values
are interpreted as multiples of 4
bytes. For example, a CLL value of
00001b means the cache line length
is 4 bytes and a cache invalidation
cycle (assertion of EADS) will be
performed every 4 bytes. A CLL
value of 00010b means the cache
line length is 8 bytes, and a cache
invalidation cycle will be performed
every 8 bytes. A CLL value of 00100
means the cache line length is 16
bytes. A value of 00000 means that
the cache line size is
“
infinite
”
. In
other words, a single EADS
assertion will be performed on the
first access at the beginning of each
bus mastership period (write
accesses only) and no subsequent
EADS assertions will be made
during this bus mastership period.
Cache
performed only during PCnet-32
controller bus master write ac-
cesses.
invalidation
cycles
are
Some CLL values are reserved (see
chart below).
The portion of the Address Bus that
will be floated at the time of an
address hold operation (AHOLD
asserted) will be determined by the
value of the Cache Line Length
register. The following chart lists all
of the legal values of CLL showing
the portion of the Address Bus that
will become floated during an
address hold operation:
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參數(shù)描述
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