參數(shù)資料
型號： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁數(shù)： 162/228頁
文件大?。?/td> 1681K
代理商： AM79C965A
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162
Am79C965A
individual descriptions of the various
DMA transfers.
PRPCNET is cleared by H_RESET
and is not affected by S_RESET or
STOP.
The default setting for this bit will be
PRPCNET = 0. This default value
reflects the nature of the CPU
’
s
handling of a HOLD request (i.e. the
CPU has lowest priority). By making
this the default setting, the PCnet-32
controller response to HOLDI is as
close as possible to the timing of the
CPU response to HOLD, so that
minimal design difficulty will be
created by inserting the PCnet-32
controller into the system as the
mediating device between the CPU
and the extension bus chipset.
8
RES
Reserved bit. Must be written as a
ONE. Will be read as a ONE.
This reserved location is SET by
H_RESET and is not affected by
S_RESET or STOP.
7
DWIO
Double Word I/O. When set, this bit
indicates that the PCnet-32
controller is programmed for DWIO
mode. When cleared, this bit
indicates that the PCnet-32
controller is programmed for Word
I/O mode. This bit affects the I/O
Resource Offset map and it affects
the defined width of the PCnet-32
controller
’
s I/O resources. See the
DWIO and WIO sections for more
details.
The PCnet-32 controller will set
DWIO if it detects a double-word
write
access to offset 10h from the
PCnet-32 controller I/O Base
Address (corresponding to the RDP
resource). A double word write
access to offset 10h is the only way
that the DWIO bit can be set. DWIO
cannot be set by a direct write to
BCR18.
Once the DWIO bit has been set to
a ONE, only a H_RESET can reset
it to a ZERO.
DWIO is
read only
by the host.
DWIO is cleared by H_RESET and
is not affected by S_RESET or
STOP.
6
BREADE Burst Read Enable. When set, this
bit enables Linear Bursting during
memory read accesses, where
Linear Bursting is defined to mean
that only the first transfer in the
current bus arbitration will contain
an address cycle. Subsequent
transfers will consist of data only.
However, the entire address bus will
still be driven with appropriate
values during the subsequent
cycles, but ADS will not be asserted.
When cleared, this bit prevents the
part from performing linear bursting
during read accesses. In no case
will the part linearly burst a
descriptor access or an initialization
access.
BREADE is cleared by H_RESET
and is not affected by S_RESET or
STOP.
Burst Read activity is not allowed
when the BCLK frequency is >33
MHz. Linear bursting is disabled in
VL-Bus systems that operate above
this frequency by connecting the
VLBEN pin to either ID(3) (for VL-
Bus version 1.0 systems) or ID(4)
AND ID(3) AND ID(1) AND ID(0) (for
VL-Bus version 1.1 or 2.0 systems).
In Am486-style systems that have
BCLK frequencies above 33 MHz,
disabling the linear burst capability
is ideally carried out through
EEPROM bit programming, since
the EEPROM programming can be
setup for a particular machine
’
s
architecture. When the VLBEN pin
has been reset to a ZERO, then the
BREADE bit will be forced to a value
of ZERO. Any attempt to change this
value by writing to the BREADE bit
location will have no effect.
5
BWRITE Burst Write Enable. When set, this
bit enables Linear Bursting during
memory write accesses, where
Linear Bursting is defined to mean
that only the first transfer in the
current bus arbitration will contain
an address cycle. Subsequent
transfers will consist of data only.
However, the entire address bus will
still be driven with appropriate
values during the subsequent
cycles, but ADS will not be asserted.
When cleared, this bit prevents the
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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