參數(shù)資料
型號(hào)： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁數(shù)： 125/228頁
文件大?。?/td> 1681K
代理商： AM79C965A
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Am79C965A
125
controller within a system. Each of these registers con-
tains control bits or status bits or both.
RAP
Register Address Port Register
CSR0
PCnet-32 Controller Status Register
CSR4
Test and Features Control
CSR112
Missed Frame Count
CSR114
RAP Register
Receive Collision Count
The RAP (Register Address Pointer) register is used to gain
access to CSR and BCR registers on board the PCnet-32
controller. The value of the RAP indicates the address of a
CSR or BCR whenever an RDP or BDP access is per-
formed. That is to say, RAP serves as a pointer to CSR and
BDP space.
As an example of RAP use, consider a read access to
CSR4. In order to access this register, it is necessary to first
load the value 0004 into the RAP by performing a write
access to the RAP offset of 12h (12h when WIO mode has
been selected, 14h when DWIO mode has been selected).
The data for the RAP write would be 0004. Then a second
access is performed on the PCnet-32 controller, this time to
the RDP offset of 10h (for either WIO or DWIO mode). The
RDP access is a read access, and since RAP has just been
loaded with the value of 0004, the RDP read will yield the
contents of CSR4. A read of the BDP at this time (offset of
16h when WIO mode has been selected, 1Ch when DWIO
mode has been selected) will yield the contents of BCR4,
since the RAP is used as the pointer into both BDP and RDP
space.
RAP: Register Address Port
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-8
RES
Reserved locations. Read and
written as zeros.
7-0
RAP
Register Address Port. The value of
these 8 bits determines which CSR
or BCR will be accessed when an I/
O access to the RDP or BDP port,
respectively, is performed. RAP is
cleared by H_RESET or S_RESET
and is unaffected by the STOP bit.
Control and Status Registers
The CSR space is accessible by performing accesses
to the RDP (Register Data Port). The particular CSR
that is read or written during an RDP access will
depend upon the current setting of the RAP. RAP
serves as a pointer into the CSR space. RAP also
serves as the pointer to BCR space, which is described
in a later section.
CSR0: PCnet-32 Controller Status
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15
ERR
Error is set by the ORing of BABL,
CERR, MISS, and MERR.
ERR remains set as long as any of
the error flags are true. ERR is read
only. Write operations are ignored.
14
BABL
Babble is a transmitter time-out
error. It indicates that the trans-
mitter has been on the channel
longer than the time required to
send the maximum length frame.
BABL will be set if 1519 bytes or
greater are transmitted. When BABL
is set, INTR is asserted if IENA = 1
and the mask bit BABLM in CSR3 is
clear. BABL assertion will set the
ERR bit.
BABL is set by the MAC layer and
cleared by writing a
“
1
”
. Writing a
“
0
”
has no effect. BABL is cleared by
H_RESET or S_RESET or setting
the STOP bit.
13
CERR
Collision Error indicates that the
collision inputs to the AUI port failed
to activate within 20 network bit
times after chip terminated
transmission (SQE Test). This
feature is a transceiver test feature.
In 10BASE-T mode CERR will be
set if a transmission is attempted
while the T-MAU is in Link Fail state.
CERR assertion will not result in an
interrupt being generated. CERR
assertion will set the ERR bit.
CERR is set by the MAC layer and
cleared by writing a
“
1
”
. Writing a
“
0
”
has no effect. CERR is cleared by
H_RESET or S_RESET or setting
the STOP bit.
12
MISS
Missed Frame is set when PCnet-32
controller has lost an incoming
receive frame resulting from a
Receive Descriptor not being
available. This bit is the only
immediate indication that receive
data has been lost since there is no
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