參數(shù)資料
型號(hào)： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁(yè)數(shù)： 61/228頁(yè)
文件大?。?/td> 1681K
代理商： AM79C965A
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Am79C965A
61
Figure 12. FIFO DMA Write
Note that A[1:0] do not exist in a 32-bit system, but both
of these bits do exist in the buffer pointers that are
passed to the PCnet-32 controller in the descriptor.
A[1:0] values will be decoded and presented on the bus
as byte enable (BE0-BE3) values during FIFO DMA
transfers.
Linear Burst DMA Transfers
Once the PCnet-32 controller has been granted bus
mastership, the PCnet-32 controller may request to
perform linear burst cycles by de-asserting the BLAST
signal. If the device being accessed wishes to support
linear bursting, then it must assert BRDY and de-assert
RDYRTN, with the same timing that RDYRTN would
normally be provided. Linear bursting is only performed
by the PCnet-32 controller if the BREADE and/or
BWRITE bits of BCR18 are set. These bits individually
enable/disable the ability of the PCnet-32 controller to
perform linear burst accesses during master read op-
erations and master write operations, respectively.
Only FIFO data transfers will make use of the linear
burst mode.
The first transfer in the linear burst will consist of both
an address and a data cycle, but subsequent transfers
will contain data only, until the LINBC upper limit of
transfers have been executed. LINBC is a value from
the BCR18 register. The linear burst
“
upper limit
”
is
created by taking the BCR18 LINBC[2:0] value and
multiplying by 4. The result is the number of transfers
that will be performed within a single linear burst
sequence.
The entire address bus will still be driven with appropri-
ate values during the data cycles. When the LINBC
upper limit of data transfers have been performed, a
new ADS may be asserted (if there is more data to be
transferred), with a new address on the A2
–
A31 pins.
Following the new ADS cycle, the linear bursting of
data will resume. Ownership of the bus will be
maintained until other variables cause the PCnet-32
controller to relinquish the bus. These variables have
been discussed in the FIFO DMA transfers section
above. They will be reviewed again within this section
of the document.
ADS
Ti
BCLK
T1
T2
T1
T2
T1
T2
A4 A31,
M/IO, D/C
A2 A3,
BE0 BE3
RDYRTN
W/R
BRDY
BLAST
D0 D31
T1
T2
T1
T2
Ti
From
PCnet-32
From
PCnet-32
From
PCnet-32
From
PCnet-32
From
PCnet-32
18219-15
相關(guān)PDF資料
PDF描述
AM79C970AKCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AVCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970 PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C965AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C970 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
AM79C970A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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