參數(shù)資料
型號： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁數(shù)： 144/228頁
文件大小： 1681K
代理商： AM79C965A
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144
Am79C965A
CSR71: Temporary Storage Upper
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
TMP8
Upper 16 bits of a Temporary
Storage location.
Read/write accessible only when
STOP bit is set.
CSR72: Receive Ring Counter
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
RCVRC
Receive Ring Counter location.
Contains a Two
’
s complement
binary number used to number the
current receive descriptor. This
counter interprets the value in
CSR76 as pointing to the first
descriptor. A counter value of zero
corresponds to the last descriptor in
the ring.
Read/write accessible only when
STOP bit is set.
CSR74: Transmit Ring Counter
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
XMTRC
Transmit Ring Counter location.
Contains a Two
’
s complement
binary number used to number the
current transmit descriptor. This
counter interprets the value in
CSR78 as pointing to the first
descriptor. A counter value of zero
corresponds to the last descriptor in
the ring.
Read/write accessible only when
STOP bit is set.
CSR76: Receive Ring Length
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
RCVRL
Receive Ring Length. Contains the
two
’
s complement of the receive
descriptor ring length. This register
is initialized during the PCnet-32
controller initialization routine based
on the value in the RLEN field of the
initialization block. However, this
register can be manually altered. the
actual receive ring length is defined
by the current value in this register.
The ring length can be defined as
any value from 1 to 65535.
Read/write accessible only when
STOP bit is set.
CSR78: Transmit Ring Length
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
XMTRL
Transmit Ring Length. Contains the
two
’
s complement of the transmit
descriptor ring length. This register
is initialized during the PCnet-32
controller initialization routine based
on the value in the TLEN field of the
initialization block. However, this
register can be manually altered.
The actual transmit ring length is
defined by the current value in this
register. The ring length can be
defined as any value from 1 to
65535.
Read/write accessible only when
STOP bit is set.
CSR80: Burst and FIFO Threshold Control
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-14 RES
Reserved locations. Read as ones
and written as zero.
13-12 RCVFW[1:0] Receive
FIFO
Watermark.
RCVFW controls the point at which
receive DMA is requested in relation
to the number of received bytes in
the receive FIFO. RCVFW specifies
the number of bytes which must be
present (once the frame has been
verified as a non-runt) before
receive DMA is requested. Note
however that in order for receive
DMA to be performed for a new
frame, at least 64 bytes must have
been received. This effectively
avoids having to react to receive
frames which are runts or suffer a
collision during the slot time (512 bit
times). If the Runt Packet Accept
feature is enabled, receive DMA will
be requested as soon as either the
RCVFW threshold is reached, or a
complete valid receive frame is
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C965AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C970 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
AM79C970A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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