參數(shù)資料
型號(hào)： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁(yè)數(shù)： 173/228頁(yè)
文件大小： 1681K
代理商： AM79C965A
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Am79C965A
173
If external loopback is used, the FCS logic must be allo-
cated to the receiver (by setting the DXMTFCS bit in
CSR15, and clearing the ADD_FCS bit in TMD1) when
using multicast addressing.
PADR
This 48-bit value represents the unique node address
assigned by the ISO 8802-3 (IEEE/ANSI 802.3) and
used for internal address comparison. PADR[0] is the
first address bit transmitted on the wire, and must be
zero. The six hex-digit nomenclature used by the ISO
8802-3 (IEEE/ANSI 802.3) maps to the PCnet-32 con-
troller PADR register as follows: the first byte comprises
PADR[7:0], with PADR[0] being the least significant bit
of the byte. The second ISO 8802-3 (IEEE/ANSI 802.3)
byte maps to PADR[15:8], again from LS bit to MS bit,
and so on. The sixth byte maps to PADR[47:40], the LS
bit being PADR[40].
MODE
The mode register in the initialization block is copied
into CSR15 and interpreted according to the
description of CSR15.
Receive Descriptors
When SSIZE32 = 0 (BCR20[8]), then the software
structures are defined to be 16 bits wide, and receive
descriptors look as shown in Table 59.
Table 59. Receive Descriptors (SSIZE32 = 0)
PCnet-32 reference names within the table above refer
to the descriptor definitions given in text below. Since
the text descriptions are for 32-bit descriptors, the table
above shows the mapping of the 32-bit descriptors into
the 16-bit descriptor space. Since 16-bit descriptors
are a subset of the 32-bit descriptors, some portions of
the 32-bit descriptors may not appear in Table 59.
When SSIZE32 = 1 (BCR 20[8]), then the software
structures are defined to be 32 bits wide, and receive
descriptors look as shown in Table 60.
Table 60. Receive Descriptors (SSIZE 32 = 1)
* NA = These 8 bits do not exist in any LANCE descriptor.
The Receive Descriptor Ring Entries (RDREs) are
composed of four receive message descriptors
(RMD0
–
RMD3). Together they contain the following
information:
I
The address of the actual message data buffer in
user (host) memory.
I
The length of that message buffer.
I
Status information indicating the condition of the
buffer. The eight most significant bits of RMD1
(RMD1[31:24]) are collectively termed the STATUS
of the receive descriptor.
RMD0
Bit
Name
Description
31-0
RBADR
RECEIVE BUFFER ADDRESS.
This field contains the address of
the receive buffer that is associated
with this descriptor.
RMD1
Bit
Name
Description
31
OWN
This bit indicates that the de-
scriptor entry is owned by the host
(OWN=0) or by the PCnet-32
controller (OWN=1). The PCnet-32
LANCE/
PCnet-ISA
Descriptor
Designation
PCnet-32
Descriptor Designation
Address
Bits 15-0
Bits 15-8
Bits 7-0
CRDA+00
RMD0
RMD0[15:0]
CRDA+02
RMD1
RMD1[31:24]
RMD0[23:16]
CRDA+04
RMD2
RMD1[15:0]
CRDA+06
RMD3
RMD2[15:0]
LANCE/PCnet-ISA
Descriptor Designation
PCnet-32
Descriptor
Designation
Address
Bits 31-24
Bits 23-16
Bits 15-8
Bits 7-0
Bits 31-0
CRDA+00
*NA
RMD1[7:0]
RMD0[15:8]
RMD0[7:0]
RMD0
CRDA+04
RMD1[15:8]
*NA
RMD2[15:8]
RMD2[7:0]
RMD1
CRDA+08
*NA
*NA
RMD3[15:8]
RMD3[7:0]
RMD2
CRDA+0C
*NA
*NA
*NA
*NA
RMD3
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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AM79C970 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
AM79C970A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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