參數(shù)資料
型號(hào)： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁(yè)數(shù)： 37/228頁(yè)
文件大?。?/td> 1681K
代理商： AM79C965A
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)當(dāng)前第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)
Am79C965A
37
Table 14. CLL Value and Floating Address Pins
BCLK
Bus Clock
Clock input that provides timing edges for all interface
signals. This clock is used to drive the system bus inter-
face and the internal buffer management unit. This
clock is NOT used to drive the network functions.
Input
BE0
–
BE3
Byte Enable
These signals indicate which bytes on the data bus are
active during read and write cycles. When BE3 is
active, the byte on D31
–
D24 is valid. BE2
–
BE0 active
indicate valid data on pins D23
–
D16, D15
–
D8, D7
–
D0,
respectively. The byte enable signals are outputs for
bus master and inputs for bus slave operations.
Input/Output
BLAST
Burst Last Output
When the BLAST signal is asserted, then the next time
that BRDY or RDYRTN is asserted, the burst cycle is
complete.
BOFF
Backoff
BOFF is monitored as an input during Bus Master ac-
cesses. When PCnet-32 controller is current local bus
master, it will float all appropriate bus mastering signals
within 1 clock period of the assertion of BOFF. When
BOFF is de-asserted, PCnet-32 controller will restart
any accesses that were suspended due to the
assertion of BOFF and then will proceed with other
scheduled accesses, if any. Register access cannot be
performed to the PCnet-32 device while BOFF is
asserted.
Input
BRDY
Burst Ready
BRDY functions as an input to the PCnet-32 controller
during bus master cycles. When BRDY is asserted dur-
ing a master cycle, it indicates to the PCnet-32
controller that the target device is accepting burst
transfers. It also serves the same function as RDYRTN
does for non-burst accesses. That is, it indicates that
the target device has accepted the data on a master
write cycle, or that the target device has presented
valid data onto the bus during master read cycles.
Input/Output
If BRDY and RDYRTN are sampled active in the same
cycle, then RDYRTN takes precedence, causing the
next transfer cycle to begin with a T1 cycle.
BRDY functions as an output during PCnet-32
controller slave cycles and is always driven inactive
(HIGH).
BRDY is floated if the PCnet-32 controller is not being
accessed as the current slave device on the local bus.
D/C
Data/Control Select
During slave accesses to the PCnet-32 controller, the
D/C pin, along with M/IO and W/R, indicates the type of
cycle that is being performed. PCnet-32 controller will
only respond to local bus accesses in which D/C is
driven HIGH by the local bus master.
Input/Output
During PCnet-32 controller bus master accesses, the
D/C pin is an output and will always be driven HIGH.
D/C is floated if the PCnet-32 controller is not the
current master on the local bus.
D0
–
D31
Data Bus
Used to transfer data to and from the PCnet-32 control-
ler to system resources via the local bus. D31
–
D0 are
driven by the PCnet-32 controller when performing bus
master writes and slave read operations. Data on D31
–
D0 is latched by the PCnet-32 controller when
performing bus master reads and slave write
operations.
Input/Output
The PCnet-32 controller will always follow Am386DX
byte lane conventions. This means that for word and
byte accesses in which PCnet-32 controller drives the
data bus (i.e. master write operations and slave read
operations) the PCnet-32 controller will produce dupli-
cates of the active bytes on the unused half of the 32-
bit data bus. Table 15 illustrates the cases in which
duplicate bytes are created.
CLL Value
Floated Portion of Address
Bus During AHOLD
00000
None
00001
A31
–
A2
00010
A31
–
A3
00011
Reserved CLL Value
00100
A31
–
A4
00101
–
00111
Reserved CLL Values
01000
A31
–
A5
01001
–
01111
Reserved CLL Values
10000
A31
–
A6
10001
–
11111
Reserved CLL Values
相關(guān)PDF資料
PDF描述
AM79C970AKCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AVCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970 PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C965AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C970 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
AM79C970A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*