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參數(shù)資料
| 型號(hào)： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 86/228頁 |
| 文件大?。?/td> | 1681K |
| 代理商： | AM79C965A |
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86
Am79C965A
Buffer Management Unit
The buffer management unit is a micro-coded state
machine which implements the initialization procedure
and manages the descriptors and buffers. The buffer
management unit operates at a speed of BCLK 2.
Initialization
PCnet-32 controller initialization includes the reading of
the initialization block in memory to obtain the
operating parameters. The initialization block must be
located on a double word (4-byte) address boundary,
regardless of the setting of the SSIZE32, (CSR58[8]/
BCR20[8]) bit. The initialization block is read when the
INIT bit in CSR0 is set. The INIT bit should be set
before or concurrent with the STRT bit to insure correct
operation. Two double-words are read during each
period of bus mastership. When SSIZE32 = 1
(CSR58[8]/ BCR20[8]), this results in a total of 4
arbitration cycles (3 arbitration cycles if SSIZE32 = 0).
Once the initialization block has been completely read
in and internal registers have been updated, IDON will
be set in CSR0, and an interrupt generated (if IENA is
set). At this point, the BMU knows where the receive
and transmit descriptor rings and hence, normal
network operations will begin.
The Initialization Block is vectored by the contents of
CSR1 (least significant 16 bits of address) and CSR2
(most significant 16 bits of address). The block
contains the user defined conditions for PCnet-32
controller operation, together with the base addresses
and length information of the transmit and receive
descriptor rings.
There is an alternative method to initialize the
PCnet-32 controller. Instead of initialization via the
initialization block in memory, data can be written
directly into the appropriate registers. Either method
may be used at the discretion of the programmer. If the
registers are written to directly, the INIT bit must not be
set, or the initialization block will be read in, thus
overwriting the previously written information. Please
refer to Appendix C for details on this alternative
method.
Re-Initialization
The transmitter and receiver sections of the PCnet-32
controller can be turned on via the initialization block
(MODE Register DTX, DRX bits; CSR15[1:0]). The
states of the transmitter and receiver are monitored by
the host through CSR0 (RXON, TXON bits). The
PCnet-32 controller should be reinitialized if the trans-
mitter and/or the receiver were not turned on during the
original initialization, and it was subsequently required
to activate them or if either section was shut off due to
the detection of an error condition (MER, UFLO, TX
BUFF error).
Re-initialization may be done via the initialization block
or by setting the STOP bit in CSR0, followed by writing
to CSR15, and then setting the START bit in CSR0.
Note that this form of restart will not perform the same
in the PCnet-32 controller as in the LANCE. In
particular, upon restart, the PCnet-32 controller
reloads the transmit and receive descriptor pointers
with their respective base addresses. This means that
the software must clear the descriptor own bits and
reset its descriptor ring pointers before the restart of
the PCnet-32 controller. The reload of descriptor base
addresses is performed in the LANCE only after
initialization, so a restart of the LANCE without
initialization leaves the LANCE pointing at the same
descriptor locations as before the restart.
Buffer Management
Buffer management is accomplished through message
descriptor entries organized as ring structures in mem-
ory. There are two rings, a receive ring and a transmit
ring. The size of a message descriptor entry is 4
double-words, or 16 bytes, when SSIZE32 = 1. The
size of a message descriptor entry is 4 words, or 8
bytes, when SSIZE32 = 0 (CSR58[8]/BCR20[8]).
Descriptor Rings
Each descriptor ring must be organized in a contiguous
area of memory. At initialization time (setting the INIT
bit in CSR0), the PCnet-32 controller reads the user-
defined base address for the transmit and receive
descriptor rings, as well as the number of entries
contained in the descriptor rings. Descriptor ring base
addresses must be on a 16-byte boundary when
SSIZE32 = 1, or on an 8-byte boundary when SSIZE32
= 0. A maximum of 128 (or 512, depending upon the
value of SSIZE32) ring entries is allowed when the ring
length is set through the TLEN and RLEN fields of the
initialization block. However, the ring lengths can be set
beyond this range (up to 65535) by writing the transmit
and receive ring length registers (CSR76, CSR78)
directly.
Each ring entry contains the following information:
1.
The address of the actual message data buffer in
user or host memory
2.
The length of the message buffer
3.
Status information indicating the condition of the
buffer
To permit the queuing and dequeuing of message buff-
ers, ownership of each buffer is allocated to either the
PCnet-32 controller or the host. The OWN bit within the
descriptor status information, either TMD or RMD (see
section on TMD or RMD), is used for this purpose.
OWN =
“
1
”
signifies that the PCnet-32 controller cur-
rently has ownership of this ring descriptor and its
associated buffer. Only the owner is permitted to
relinquish ownership or to write to any field in the
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相關(guān)代理商/技術(shù)參數(shù) |
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