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參數(shù)資料
| 型號： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 19/228頁 |
| 文件大?。?/td> | 1681K |
| 代理商： | AM79C965A |
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Am79C965A
19
LDEV
Local Device
LDEV is driven by the PCnet-32 controller when it
recognizes an access to PCnet-32 controller I/O space.
Such recognition is dependent upon a valid sampled
ADS strobe plus valid M/IO, D/C and ADR31
–
ADR5
values.
LEADS
Local External Address Strobe
During VL-Bus master write and read accesses the
LEADS pin will be asserted on every T1 cycle as is
specified in the VESA VL-Bus specification, regardless
the settings of the GCIC bit of BCR18 and the CLL bits
BCR18.
LGNT
Local Bus Grant
When LGNT is asserted and LREQ is being asserted
by the PCnet-32 controller, the PCnet-32 controller as-
sumes ownership of the VL bus.
Output
Output
Input
Note that this pin changes polarity when Local Bus
mode has been selected (see pin description of HLDA
in 486 Local Bus Interface section).
LGNTO
Local Grant Out
This signal is multiplexed with the TCK pin, and is avail-
able only when the Multi-Interrupt mode has been se-
lected with the JTAGSEL pin.
Output
An additional local bus master may daisy-chain its
LGNT
signal through the PCnet-32 controller
LGNTO
pin
.
The
PCnet-32 controller will deliver a LGNTO signal the
additional local bus master whenever the PCnet-32
controller receives a LGNT from the arbitration logic,
but is not simultaneously requesting the bus internally.
The second local bus master must connect its LREQ
output to the LREQI input of the PCnet-32 controller in
order to complete the local bus daisy-chain arbitration
control.
When SLEEP is not asserted, daisy chain arbitration
signals that pass through the PCnet-32 controller will
experience a one-clock delay from input to output (i.e.
LREQI to LREQ and LGNT to LGNTO).
While SLEEP is asserted (either in
snooze
mode or
coma
mode), if the PCnet-32 controller is configured
for daisy chain (LREQI and LGNTO signals have been
selected with the JTAGSEL pin), then the system arbi-
tration signal LGNT will be passed directly to the daisy-
chain signal LGNTO without experiencing a one-clock
delay. However, some combinatorial delay will be intro-
duced in this path.
Note that this pin changes polarity when Local Bus
mode has been selected (see pin description of
HLDAO 486 Local Bus Interface section).
LRDY
Local Ready
LRDY functions as an output from the PCnet-32
controller during PCnet-32 controller slave cycles.
During PCnet-32 controller slave read cycles, LRDY is
asserted to indicate that valid data has been presented
on the data bus. During PCnet-32 controller slave write
cycles, LRDY is asserted to indicate that the data on
the data bus has been internally latched. LRDY will be
asserted low for one clock period when the PCnet-32
controller wishes to terminate the cycle. LRDY is then
driven high for one-half of one clock period before
being released.
Output
LRDY is floated if the PCnet-32 controller is not the
current slave on the local bus.
LREQ
Local Bus Request
LREQ is used by the PCnet-32 controller to gain control
of the VL-Bus and become the active VL Bus Master.
LREQ is active low. Once asserted, LREQ remains ac-
tive until LGNT has become active, independent of
subsequent assertion of SLEEP or setting of the STOP
bit or access to the S_RESET port (offset 14h).
Output
Note that this pin changes polarity when Local Bus
mode has been selected (see pin description of HOLD
in 486 Local Bus Interface section).
LREQI
Local Bus Request In
This signal is multiplexed with the TDO pin, and is
available only when the Multi-Interrupt mode has been
selected with the JTAGSEL pin.
Input
An additional local bus master may daisy-chain its bus
hold request signal through the PCnet-32 controller
LREQI pin. The PCnet-32 controller will convey the
LREQI request to the arbitration logic via the PCnet-32
controller LREQ output. The second local bus master
must connect its LGNT input to the LGNTO output of
the PCnet-32 controller in order to complete the local
bus daisy-chain arbitration control.
When SLEEP is not asserted, daisy chain arbitration
signals that pass through the PCnet-32 controller will
experience a one-clock delay from input to output (i.e.
LREQI to LREQ and LGNT to LGNTO).
While SLEEP is asserted (either in
snooze
mode or
coma
mode), if the PCnet-32 controller is configured
for daisy chain (LREQI and LGNTO signals have been
selected with the JTAGSEL pin), then the daisy-chain
signal LREQI will be passed directly to the system arbi-
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AM79C965AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
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| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
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