參數(shù)資料
型號: Am79C965A
廠商: Advanced Micro Devices, Inc.
英文描述: PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述: PCnet?-32單芯片32位以太網(wǎng)控制器
文件頁數(shù): 149/228頁
文件大?。?/td> 1681K
代理商: AM79C965A
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Am79C965A
149
then a MERR will be indicated in
CSR0, bit 11, and an interrupt may
be generated, depending upon the
setting of the MERRM bit (CSR3, bit
11) and IENA bit (CSR0[6]).
The value in this register is inter-
preted as a number of XTAL1
3
2
clock periods. (i.e. the value in this
register is given in 0.1 ms in-
crements.) For example, the value
0200h (512 decimal) will cause a
MERR to be indicated after 51.2 μs
of bus latency.
A value of zero will allow an infi-
nitely long bus latency. i.e. a value of
zero will never give a bus time-out
error. A non-zero value is interpreted
as an unsigned number of BCLK
cycles.
This register is set to 0200 by
H_RESET or S_RESET and is
unaffected by STOP.
Read/write accessible only when
STOP bit is set.
CSR104: SWAP Register Lower
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
SWAP
This register performs word and
byte swapping depending upon if
32-bit or 16-bit internal write
operations are performed. This
register is used internally by the BIU/
BMU as a word or byte swapper.
The register is externally accessible
for test reasons only. CSR104 holds
the lower 16 bits and CSR105 holds
the upper 16 bits.
Read/write accessible only when
STOP bit is set.
CSR105: SWAP Register Upper
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
SWAP
This register performs word and
byte swapping depending upon if
32-bit or 16-bit internal write
operations are performed. This
register is used internally by the BIU/
BMU as a word or byte swapper.
The register is externally accessible
for test reasons only. CSR104 holds
the lower 16 bits and CSR105 holds
the upper 16 bits.
Read/write accessible only when
STOP bit is set.
CSR108: Buffer Management Scratch Lower
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
BMSCR
The Buffer Management Scratch
register is used for assembling
Receive and Transmit Status. This
register is also used as the primary
scan
register
Management Test Modes. BMSCR
register is undefined until written.
for
Buffer
Read/write accessible only when
STOP bit is set.
CSR109: Buffer Management Scratch Upper
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
BMSCR
The Buffer Management Scratch
register is used for assembling
Receive and Transmit Status. This
register is also used as the primary
scan
register
Management Test Modes. BMSCR
register is undefined until written.
for
Buffer
Read/write accessible only when
STOP bit is set.
CSR112: Missed Frame Count
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
MFC
Missed Frame Count. Indicates the
number of missed frames.
MFC will roll over to a count of zero
from the value 65535. The MFCO bit
of CSR4 (bit 8) will be set each time
that this occurs.
This register is always readable and
is cleared by H_RESET or
S_RESET or STOP.
A write to this register performs an
increment when the ENTST bit in
CSR4 is set.
CSR114: Receive Collision Count
Bit
Name
Description
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