參數(shù)資料
型號： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁數(shù)： 39/228頁
文件大?。?/td> 1681K
代理商： AM79C965A
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Am79C965A
39
experience a one-clock delay from input to output (i.e.
HOLDI to HOLD and HLDA to HLDAO).
While SLEEP is asserted (either in
snooze
mode or
coma
mode), if the PCnet-32 controller is configured
for a daisy chain (HOLDI and HLDAO signals have
been selected with the JTAGSEL pin), then the daisy-
chain signal HOLDI will be passed directly to the
system arbitration signal HOLD without experiencing a
one-clock delay. However, some combinatorial delay
will be introduced in this path.
If Multi-Interrupt mode has been selected and the
daisy-chain arbitration feature is not used, then the
HOLDI input should be tied to VSS through a resistor.
Note that this pin changes polarity when VL mode has
been selected (see pin description of LREQI in VESA
VL-Bus Interface section).
INTR1
–
INTR4
Interrupt Request
An attention signal which indicates that one or more of
the following status flags is set: BABL, MISS, MERR,
RINT, IDON, MFCO, RCVCCO, TXSTRT, or JAB. Each
of these status flags has a mask bit which allows for
suppression of INTR assertion. These flags have the
meaning shown in Table 16.
Output
Table 16. Status Flags
Note that there are four possible interrupt pins,
depending upon the mode that has been selected with
the JTAGSEL pin. Only one interrupt pin may be used
at one time. The active interrupt pin is selected by pro-
gramming the interrupt select register (BCR21). The
default setting of BCR121will select interrupt INTR1 as
the active interrupt. Note that BCR21 is EEPROM-
programmable. Inactive interrupt pins are floated.
The polarity of the interrupt signal is determined by the
INTLEVEL bit of BCR2. The interrupt pins may be
programmed for level-sensitive or edge-sensitive
operation.
PCnet-32 controller interrupt pins will be floated at
H_RESET and will remain floated until either the
EEPROM has been successfully read, or, following an
EEPROM read failure, a Software Relocatable Mode
sequence has been successfully executed.
LDEV
Local Device
LDEV is driven by the PCnet-32 controller when it
recognizes an access to PCnet-32 controller I/O space.
Such recognition is dependent upon a valid sampled
ADS strobe plus valid M/IO, D/C and A31
–
A5 values.
M/IO
Memory I/O Select
During slave accesses to the PCnet-32 controller, the
M/IO pin, along with D/C and W/R, indicates the type of
cycle that is being performed. PCnet-32 controller will
only respond to local bus accesses in which M/IO is
sampled as a zero by the PCnet-32 controller.
Output
Input/Output
During PCnet-32 controller bus master accesses, the
M/IO pin is an output and will always be driven high.
M/IO is floated if the PCnet-32 controller is not the cur-
rent master on the local bus.
RESET
System Reset
When RESET is asserted high and the LB/VESA pin
has been tied to VDD, then the PCnet-32 controller
performs an internal system reset of the type
H_RESET (HARDWARE_ RESET). The RESET pin
must be held for a minimum of 30 BCLK periods. While
in the H_RESET state, the PCnet-32 controller will float
or de-assert all outputs.
Input
Note that this pin changes polarity when VL mode has
been selected (see pin description of RESET in VESA
VL-Bus Interface section).
RDY
Ready
RDY functions as an output from the PCnet-32 control-
ler during PCnet-32 controller slave cycles. During
PCnet-32 controller slave read cycles, RDY is asserted
to indicate that valid data has been presented on the
data bus. During PCnet-32 controller slave write
cycles, RDY is asserted to indicate that the data on the
data bus has been internally latched. RDY is asserted
for one BCLK period. RDY is then driven high for one-
half of one clock period before being released.
Output
RDY is floated if the PCnet-32 controller is not the cur-
rent slave on the local bus.
BABL
Babble (CSR0, bit 14)
MISS
Missed Frame (CSR0, bit 12)
MERR
Memory Error (CSR0, bit 11)
RINT
Receive Interrupt (CSR0, bit 10)
IDON
Initialization Done (CSR0, bit 8)
MFCO
Missed Packet Count Overflow
(CSR4, bit 9)
RCVCCO
Receive Collision Count Overflow
(CSR4, bit 5)
TXSTRT
Transmit Start (CSR4, bit 3)
JAB
Jabber (CSR4, bit 1)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C965AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C970 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
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AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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