參數(shù)資料
型號： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁數(shù)： 150/228頁
文件大?。?/td> 1681K
代理商： AM79C965A
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150
Am79C965A
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-0
RCC
Receive Collision Count. Indicates
the total number of collisions
encountered by the receiver since
the last reset of the counter.
RCC will roll over to a count of zero
from the value 65535. The
RCVCCO bit of CSR4 (bit 5) will be
set each time that this occurs.
The RCC value is read accessible at
all times, regardless of the value of
the STOP bit. Write operations are
ignored. RCC is cleared by
H_RESET or S_RESET or by
setting the STOP bit.
A write to this register performs an
increment when the ENTST bit in
CSR4 is set.
CSR122: Receive Frame Alignment Control
Bit
Name
Description
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-1
RES
Reserved locations, written as zeros
and read as undefined.
0
RCVALGN Receive Frame Align. When set,
this bit forces the data field of ISO
8802-3 (IEEE/ANSI 802.3) frames
to align to 0 MOD 4 address
boundaries (i.e. double word aligned
addresses). It is important to note
that this feature will only function
correctly if all receive buffer
boundaries are double-word aligned
and all receive buffers have 0 MOD
4 lengths. In order to accomplish the
data alignment, the PCnet-32
controller simply inserts two bytes of
random data at the beginning of the
receive packet (i.e. before the ISO
8802-3 (IEEE/ ANSI 802.3)
destination address field). The
MCNT field reported to the receive
descriptor will not include the extra
two bytes.
RCVALGN is cleared by H_RESET
or S_RESET and is not affected by
STOP.
Read/write accessible only when
STOP bit is set.
CSR124: Buffer Management Test
Bit
Name
Description
This register is used to place the
BMU/BIU into various test mode to
support Test/Debug. This register is
writable only when the ENTST bit in
CSR4 and the STOP bit of CSR0 are
both set. The functions controlled by
this register are enabled only if the
ENTST bit is set.
ENTST should be set before
anything in CSR124 can be pro-
grammed, including RUNTACC.
ENTST must be reset after writing to
CSR124 before writing to any other
register. If it is done, the PCnet-32
controller will not run.
All bits in this register or cleared by
H_RESET or S_RESET and are not
affected by STOP.
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15-5
RES
Reserved locations. Read and
written as zero.
4
GPSIEN This bit places the PCnet-32
controller in the GPSI mode. This
mode will reconfigure the System
Interface Address Pins so that the
GPSI port is exposed. This allows
bypassing the MENDEC T-MAU
logic. The GPSI mode may also be
enabled by test shadow bits setting
of BCR18, bits 4 and 3 as in Table
44.
See Table 45 for pin reconfiguration
in GPSI mode.
Note that when the GPSI mode is
invoked, only the lower 24 bits of the
address bus are available. During
Software Relocatable Mode the
LED2 pin must be pulled LOW.
IOAW24 (BCR21[8]) must be set to
allow slave operations. During
master accesses in GPSI mode, the
PCnet-32 controller will not drive the
upper 8 bits of the address bus with
address information.
3
RPA
Runt Packet Accept. This bit forces
the receive logic to accept runt
packets (packets shorter than 64
bytes). The state of the RPA bit can
be changed only when the device is
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參數(shù)描述
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