參數(shù)資料
型號(hào): Am79C965A
廠商: Advanced Micro Devices, Inc.
英文描述: PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述: PCnet?-32單芯片32位以太網(wǎng)控制器
文件頁(yè)數(shù): 158/228頁(yè)
文件大?。?/td> 1681K
代理商: AM79C965A
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158
Am79C965A
network that has passed the ad-
dress match function for this node.
All address matching modes are
included: Physical, Logical filtering,
Promiscuous, Broadcast, and EADI.
A value of 0 disables the signal. A
value of 1 enables the signal.
4
XMTE
Transmit status Enable. Indicates
PCnet-32 controller transmit activity.
A value of 0 disables the signal. A
value of 1 enables the signal.
3
RXPOLE Receive Polarity status Enable.
Indicates the current Receive
Polarity condition on the Twisted
Pair interface. A value of ONE
indicates that the polarity of the
RXD± pair has been reversed. A
value of ZERO indicates that the
polarity of the RXD± pair has not
been reversed.
Receive polarity indication is valid
only if the LNKST bit of BCR4
indicates link PASS status.
A value of 0 disables the signal. A
value of 1 enables the signal.
2
RCVE
Receive status Enable. Indicates
receive activity on the network.
A value of 0 disables the signal. A
value of 1 enables the signal.
1
JABE
Jabber status Enable. Indicates that
the PCnet-32 controller is jabbering
on the network.
A value of 0 disables the signal. A
value of 1 enables the signal.
0
COLE
Collision status Enable. Indicates
collision activity on the network.
When the AUI port is selected,
collision activity during the 4.0 ms
internal following a transmit
completion (SQE internal) will not
activate the LEDOUT bit.
A value of 0 disables the signal. A
value of 1 enables the signal.
BCR7: LED3 Status
Bit
Name
Description
BCR7 controls the function(s) that
the LEDPRE3 pin displays. Multiple
functions can be simultaneously
enabled on this LED pin. The LED
display will indicate the logical OR of
the enabled functions. BCR7
defaults to Transmit Status (XMT)
with pulse stretcher enabled (PSE =
1) and is fully programmable.
The default setting after H_RESET
for the LED3 register is 0090h. The
LED3 register value is unaffected by
S_RESET or STOP.
31-16 RES
Reserved locations. Written as
zeros and read as undefined.
15
LEDOUT This bit indicates the current (non-
stretched) value of the LED output
pin. A value of ONE in this bit
indicates that the OR of the enabled
signals is true.
The logical value of the LEDOUT
status signal is determined by the
settings of the individual Status
Enable bits of the LED register (Bits
11-8 and 5-0).
This bit is READ only by the host,
and is unaffected by H_RESET
S_RESET or STOP.
This bit is valid only if the network
link status is PASS.
14
LEDPOL LED Polarity. When this bit has the
value ZERO, then the LED pin will
be driven to a LOW level whenever
the OR of the enabled signals is true
and the LED pin will be floated and
allowed to float high whenever the
OR of the enabled signals is false
(i.e. the LED output will be an Open
Drain output and the output value
will be the inverse of the LEDOUT
status bit).
When this bit has the value ONE,
then the LED pin will be driven to a
HIGH level whenever the OR of the
enabled signals is true and the LED
pin will be driven to a LOW level
whenever the OR of the enabled
signals is false (i.e. the LED output
will be a Totem Pole output and the
output value will be the same
polarity as the LEDOUT status bit).
The setting of this bit will not affect
the polarity of the LEDOUT bit for
this register.
13
LEDDIS
LED Disable. This bit is used to
disable the LED output. When
LEDDIS has the value ONE, then
the LED output will always be
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