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參數(shù)資料
| 型號： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 120/228頁 |
| 文件大小： | 1681K |
| 代理商： | AM79C965A |
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Am79C965A
Receive frames which have a length field of 46 bytes or
greater will be passed to the host unmodified.
Note that for some network protocols, the value passed
in the Ethernet Type and/or 802.3 Length field is not
compliant with either standard and may cause
problems.
Figure 36 shows the byte/bit ordering of the received
length field for an 802.3 compatible frame format.
Receive FCS Checking
Reception and checking of the received FCS is per-
formed automatically by the PCnet-32 controller. Note
that if the Automatic Pad Stripping feature is enabled,
the FCS for padded frames will be verified against the
value computed for the incoming bit stream including
pad characters, but the FCS value for a padded frame
will not be passed to the host. If an FCS error is
detected in any frame, the error will be reported in the
CRC bit in RMD1.
Figure 36. ISO 8802.3 (IEEE/ANSI 802.3) Data Frame
Receive Exception Conditions
Exception conditions for frame reception fall into two
distinct categories: Those which are the result of
normal network operation, and those which occur due
to abnormal network and/or host related events.
Normal events which may occur and which are handled
autonomously by the PCnet-32 controller are basically
collisions within the slot time and automatic runt packet
rejection. The PCnet-32 controller will ensure that colli-
sions which occur within 512 bit times from the start of
reception (excluding preamble) will be automatically
deleted from the receive FIFO with no host
intervention. The receive FIFO will delete any frame
which is composed of fewer than 64 bytes provided that
the Runt Packet Accept (RPA bit in CSR124) feature
has not been enabled. This criterion will be met
regardless of whether the receive frame was the first
(or only) frame in the FIFO or if the receive frame was
queued behind a previously received message.
Abnormal network conditions include:
I
FCS error
I
Late collision
Host-related receive exception conditions include
MISS, BUFF, and OFLO. These are described in the
BMU section.
Loopback Operation
Loopback is a mode of operation intended for system
testing. In this mode the transmitter and receiver are
both operating at the same time so that the controller
receives its own transmissions. The controller provides
two types of internal loopback and one type of external
loopback. In internal loopback mode the transmitter
Preamble
1010....1010
Sync
10101011
Destination
Address
Source
Address
Length
LLC
Data
Pad
FCS
4
Bytes
46
1500
Bytes
2
Bytes
6
Bytes
6
Bytes
8
Bits
56
Bits
Start of Frame
at Time = 0
Increasing Time
Bit
0
Bit
7
Bit
0
Bit
7
Most
Significant
Byte
Least
Significant
Byte
1
1500
Bytes
45
0
Bytes
18219-43
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C965AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
| AM79C970 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C970A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
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