參數(shù)資料
型號(hào): Am79C965A
廠商: Advanced Micro Devices, Inc.
英文描述: PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述: PCnet?-32單芯片32位以太網(wǎng)控制器
文件頁(yè)數(shù): 18/228頁(yè)
文件大?。?/td> 1681K
代理商: AM79C965A
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18
Am79C965A
INTR1
INTR4
Interrupt Request
An attention signal which indicates that one or more of
the following status flags is set: BABL, MISS,
MERR,RINT, IDON, MFCO, RCVCCO, TXSTRT, or
JAB. Each of these status flags has a mask bit which
allows for suppression of INTR assertion. These flags
have the meaning shown in Table 7.
Output
Table 7. Status Flags
Note that there are four possible interrupt pins,
depending upon the mode that has been selected with
the JTAGSEL pin. Only one interrupt pin may be used
at one time. The active interrupt pin is selected by pro-
gramming the interrupt select register (BCR21). The
default setting of BCR121will select interrupt INTR1 as
the active interrupt. Note that BCR21 is EEPROM-pro-
grammable. Inactive interrupt pins are floated. The
polarity of the interrupt signal is determined by the
INTLEVEL bit of BCR2. The interrupt pins may be
programmed for level-sensitive or edge-sensitive
operation. PCnet-32 controller interrupt pins will be
floated at H_RESET and will remain floated until either
the EEPROM has been successfully read, or, following
an EEPROM read failure, a Software Relocatable
Mode sequence has been successfully executed.
LBS16
Local Bus Size 16
BS16 is sampled during PCnet-32 controller bus
mastering activity to determine if the target device on
the VL-Bus is 32 or 16 bits in width. If the LBS16 signal
is sampled active at least one clock period before the
assertion of LRDY during a PCnet-32 controller bus
master transfer, then the PCnet-32 controller will
convert a single 32-bit transfer into two 16-bit transfers.
Not all 32-bit transfers need to be split into two 16-bit
transfers. Table 8 shows the sequence of transfers that
will be executed for each possible 32-bit bus transfer
that encounters a proper assertion of the LBS16 signal.
Input
Table 8. Data Transfer Sequence from 32-Bit Wide to 16-Bit Wide
NR = No second access Required for these cases.
During accesses in which PCnet-32 controller is acting
the VL-Bus target device, the LBS16 signal will not be
driven. In this case, it is expected that the VL-Bus
required pull-up device will bring the LBS16 signal to an
inactive level and the PCnet-32 controller will be seen
by the VL-Bus master as a 32-bit peripheral.
LCLK
Local Clock
LCLK is a 1x clock that follows the same phase as a
486-type CPU clock. LCLK is always driven by the sys-
tem logic or the VL-Bus controller to all VL-Bus masters
and targets. The rising edge of the clock signifies the
change of CPU states, and hence, the change of
PCnet-32 controller states.
Input
BABL
Babble (CSR0, bit 14)
MISS
Missed Frame (CSR0, bit 12)
MERR
Memory Error (CSR0, bit 11)
RINT
Receive Interrupt (CSR0, bit 10)
IDON
Initialization Done (CSR0, bit 8)
MFCO
Missed Packet Count Overflow
(CSR4, bit 9)
RCVCCO
Receive Collision Count Overflow
(CSR4, bit 5)
TXSTRT
Transmit Start (CSR4, bit 3)
JAB
Jabber (CSR4, bit 1)
Current Access
Next with LBS16
BE3
BE2
BE1
BE0
BE3
BE2
BE1
BE0
1
1
1
0
NR
1
1
0
0
NR
1
0
0
0
1
0
1
1
0
0
0
0
0
0
1
1
1
1
0
1
NR
1
0
0
1
1
0
1
1
0
0
0
1
0
0
1
1
1
0
1
1
NR
0
0
1
1
NR
0
1
1
1
NR
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