參數(shù)資料
型號： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網控制器
文件頁數(shù)： 20/228頁
文件大?。?/td> 1681K
代理商： AM79C965A
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Am79C965A
tration signal LREQ without experiencing a one-clock
delay. However, some combinatorial delay will be intro-
duced in this path.
Multi-Interrupt mode has been selected and the daisy-
chain arbitration feature is not used, then the LREQI
input should be tied to
V
DD
.
Note that this pin changes polarity when Local
Busmode has been selected (see pin description of
HOLDI in 486 Local Bus Interface section).
M/IO
Memory I/O Select
During slave accesses to the PCnet-32 controller, the
M/IO pin, along with D/C and W/R, indicates the type
cycle that is being performed. PCnet-32 controller will
only respond to local bus accesses in which M/IO
sampled as a zero by the PCnet-32 controller.
Input/Output
During PCnet-32 controller bus master accesses, the
M/IO pin is an output and will always be driven high.
M/IO is floated if the PCnet-32 controller is not the cur-
rent master on the local bus.
RDYRTN
Ready Return
RDYRTN functions as an input to the PCnet-32 control-
ler. RDYRTN is used to terminate all master accesses
performed by the PCnet-32 controller, except that
linear burst transfers may also be terminated with the
BRDY signal. RDYRTN is used to terminate slave read
accesses to PCnet-32 controller I/O space.
Input
When asserted during slave read accesses to
PCnet-32 controller I/O space, RDYRTN indicates that
the bus mastering device has seen the LRDY that was
generated by the PCnet-32 controller and has
accepted the PCnet-32 controller slave read data.
Therefore, PCnet-32 controller will hold slave read data
on the bus until it synchronously samples the RDYRTN
input as active low. The PCnet-32 controller will not
hold LRDY valid asserted during this time. The duration
of the LRDY pulse generated by the PCnet-32
controller will always be a single LCLK cycle.
RDYRTN is ignored during slave write accesses
PCnet-32 controller I/O space. Slave write accesses
PCnet-32 controller I/O space are considered termi-
nated by the PCnet-32 controller at the end of the cycle
during which the PCnet-32 controller issues an active
RDY.
In systems where both a LRDY and RDYRTN (or
equivalent) signals are provided, then LRDY must not
be tied to RDYRTN. Most systems now provide for local
device ready input to the memory controller that
separate from the CPU READY signal. This second
READY signal is usually labeled as READYIN. This
signal should be connected to the PCnet-32 controller
LRDY signal. The CPU READY signal should be con-
nected to the PCnet-32 controller RDYRTN pin.
In systems where only one READY signal is provided,
then the PCnet-32 controller LRDY output may be tied
the PCnet-32 controller RDYRTN input.
RESET
System Reset
When RESET is asserted low and the LB/VESA pin
has been tied to VSS, then the PCnet-32 controller
performs an internal system reset of the H_RESET
type (HARDWARE_ RESET). The RESET pin must be
held for a minimum of 30 LCLK periods when VL mode
has been selected. While in the H_RESET state, the
PCnet-32 controller will float or de-assert all outputs.
W/R
Write/Read Select
During slave accesses to the PCnet-32 controller, the
W/R pin, along with D/C and M/IO, indicates the type of
cycle that is being performed.
Input
Input/Output
During PCnet-32 controller bus master accesses, the
W/R pin is an output.
W/R is floated if the PCnet-32 controller is not the cur-
rent master on the local bus.
WBACK
Write Back
WBACK is monitored as in input during VL-Bus Master
Accesses. When PCnet-32 controller is current VL-Bus
master, the PCnet-32 controller will float all appropriate
bus mastering signals within 1 clock period of the
assertion of WBACK. When WBACK is de-asserted,
PCnet-32 controller will re-execute any accesses that
were suspended due to the assertion of WBACK and
then will proceed with other scheduled accesses, if any.
Input
Register access cannot be performed to the PCnet-32
device while WBACK is asserted.
Board Interface
LED1
LED1
This pin is shared with the EESK function. When
operating as LED1, the function and polarity on this pin
are programmable through BCR5. The LED1 output
from the PCnet-32 controller is capable of sinking the
necessary 12 mA of current to drive an LED directly.
Output
The LED1 pin is also used during EEPROM Auto-
detection to determine whether or not an EEPROM is
present at the PCnet-32 controller microwire interface.
At the trailing edge of RESET, this pin is sampled to
determine the value of the EEDET bit in BCR19. A
sampled HIGH value means that an EEPROM is
present, and EEDET will be set to ONE. A sampled
相關PDF資料
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相關代理商/技術參數(shù)
參數(shù)描述
AM79C965AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C970 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
AM79C970A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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