參數(shù)資料
型號(hào)： Am79C965A
廠商： Advanced Micro Devices, Inc.
英文描述： PCnet?-32 Single-Chip 32-Bit Ethernet Controller
中文描述： PCnet？-32單芯片32位以太網(wǎng)控制器
文件頁(yè)數(shù)： 45/228頁(yè)
文件大?。?/td> 1681K
代理商： AM79C965A
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)當(dāng)前第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)
Am79C965A
45
BASIC FUNCTIONS
System Bus Interface Function
The PCnet-32 controller is designed to operate as a
Bus Master during normal operations. Some slave
accesses to the PCnet-32 controller are required in
normal operations as well. Initialization of the PCnet-32
controller is achieved through a combination of Bus
Slave accesses, Bus Master accesses and an optional
read of a serial EEPROM that is performed by the
PCnet-32 controller. The EEPROM read operation is
performed through the microwire interface. The ISO
8802-3 (IEEE/ANSI 802.3) Ethernet Address may
reside within the serial EEPROM. Some PCnet-32
controller configuration registers may also be
programmed by the EEPROM read operation.
The address PROM, on-chip board-configuration
registers, and the Ethernet controller registers occupy
32 bytes of I/O space which can be located by
modifying the I/O base address register. The default
base address can be written to the EEPROM. The
PCnet-32 controller will automatically read the I/O
Base Address from the EEPROM after H_RESET, or at
any time that the software requests that the EEPROM
should be read. When no EEPROM is attached to the
serial microwire interface, the PCnet-32 controller
detects the condition, and enters Software Relocatable
Mode. While in Software Relocatable Mode, the
PCnet-32 controller will not respond to any bus
accesses, but will snoop the bus for accesses to I/O
address 378h. When a successfully executed and
uninterrupted sequence of write operations is seen at
this location, the PCnet-32 controller will accept the
next sequence of accesses as carrying I/O Base
Address relocation and interrupt pin programming
information. After this point, the PCnet-32 controller will
begin to respond directly to accesses directed toward
offsets from the newly loaded I/O Base Address. This
scheme allows for jumperless relocatable I/O
implementations.
Software Interface
The software interface to the PCnet-32 controller is di-
vided into two parts. One part is the direct access to the
I/O resources of the PCnet-32 controller. The PCnet-32
controller occupies 32 bytes of I/O space that must be-
gin on a 32-byte block boundary. The I/O Base Address
can be changed to any 32-bit quantity that begins on a
32-byte block boundary through the function of the
Software Relocatable Mode. It can also be changed to
any 32-bit value that begins on a 32-byte block
boundary through the automatic EEPROM read
operation that occurs immediately after the H_RESET
function has completed. This read operation
automatically alters the I/O Base Address of the
PCnet-32 controller.
The 32-byte I/O space is used by the software to pro-
gram the PCnet-32 controller operating mode, to
enable and disable various features, to monitor
operating status and to request particular functions to
be executed by the PCnet-32 controller.
The other portion of the software interface is the
descriptor and buffer areas that are shared between
the software and the PCnet-32 controller during normal
network operations. The descriptor area boundaries
are set by the software and do not change during
normal network operations. There is one descriptor
area for receive activity and there is a separate area for
transmit activity. The descriptor space contains
relocatable pointers to the network packet data and it is
used to transfer packet status from the PCnet-32
controller to the software. The buffer areas are
locations that hold packet data for transmission or that
accept packet data that has been received.
Network Interfaces
The PCnet-32 controller can be connected to an 802.3
network via one of two network interfaces. The Attach-
ment Unit Interface (AUI) provides an ISO 8802-3
(IEEE/ANSI 802.3) compliant differential interface to a
remote MAU or an on-board transceiver. The
10BASE-T interface provides a twisted-pair Ethernet
port. While in auto-selection mode, the interface in use
is determined by an auto-sensing mechanism which
checks the link status on the 10BASE-T port. If there is
no active link status, then the device assumes an AUI
connection.
DETAILED FUNCTIONS
Bus Interface Unit
The bus interface unit is built of several state machines
that run synchronously to BCLK. One bus interface unit
state machine handles accesses where the PCnet-32
controller is the bus slave, and another handles ac-
cesses where the PCnet-32 controller is the bus
master. All inputs are synchronously sampled
except
ADS, M/IO, D/C, W/R and the A[31:5] bus when this
bus is an input to the PCnet-32 controller. All outputs
are synchronously generated on the rising edge of
BCLK
with the following exceptions
:
LDEV is generated asynchronously.
RDY is
driven/floated
on falling edges of BCLK, but will
change state on rising edges of BCLK.
相關(guān)PDF資料
PDF描述
AM79C970AKCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AVCW PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970 PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C965AWW WAF 制造商:Advanced Micro Devices 功能描述:
AM79C970 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
AM79C970A 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*