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參數(shù)資料
| 型號： | Am79C965A |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnet?-32 Single-Chip 32-Bit Ethernet Controller |
| 中文描述： | PCnet？-32單芯片32位以太網(wǎng)控制器 |
| 文件頁數(shù)： | 43/228頁 |
| 文件大小： | 1681K |
| 代理商： | AM79C965A |
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Am79C965A
43
External Address Detection Interface
The EADI interface is enabled through BCR2, bit 3
(EADISEL).
EAR
External Address Reject Low Input
An EADI input signal. The incoming frame will be
checked against the internally active address detection
mechanisms and the result of this check will be OR
’
d
with the value on the EAR pin. The EAR pin is defined
as REJECT.
See the EADI section for details regarding the function
and timing of this signal.
Note that this pin is multiplexed with the INTR2 pin.
SFBD
Start Frame
–
Byte Delimiter
Start Frame
–
Byte Delimiter Enable. EADI output
signal. An initial rising edge on this signal indicates that
a start of frame delimiter has been detected. The serial
bit stream will follow on the SRD signal, commencing
with the destination address field. SFBD will go high for
4 bit times (400 ns) after detecting the second
“
1
”
in the
SFD (Start of Frame Delimiter) of a received frame.
SFBD will subsequently toggle every 400 ns (1.25 MHz
frequency) with each rising edge indicating the first bit
of each subsequent byte of the received serial bit
stream. SFBD will be inactive during frame
transmission.
Output
Note that this pin is multiplexed with the LED1 pin.
SRD
Serial Receive Data
An EADI output signal. SRD is the decoded NRZ data
from the network. This signal can be used for external
address detection. Note that when the 10BASE-T port
is selected, transitions on SRD will only occur during
receive activity. When the AUI port is selected, transi-
tions on SRD will occur during both transmit and re-
ceive activity.
Output
Note that this pin is multiplexed with the LEDPRE3 pin.
SRDCLK
Serial Receive Data Clock
An EADI output signal. Serial Receive Data is synchro-
nous with reference to SRDCLK. Note that when the
10BASE-T port is selected, transitions on SRDCLK will
only occur during receive activity. When the AUI port is
selected, transitions on SRDCLK will occur during both
transmit and receive activity.
Output
Note that this pin is multiplexed with the LED2 pin.
General Purpose Serial Interface
The GPSI interface is selected through the PORTSEL
bits of the Mode register (CSR15) and enabled through
the TSTSHDW[1] bit (BCR18) or the GPSIEN bit
(CSR124).
Note that when GPSI test mode is invoked, slave ad-
dress decoding must be restricted to the lower 24 bits
of the address bus by setting the IOAW24 bit in BCR2
and by pulling LED2 LOW during Software Reloactable
Mode. The upper 8 bits of the address bus will always
be considered matched when examining incoming I/O
addresses. During master accesses while in GPSI
mode, the PCnet-32 controller will not drive the upper
8 bits of the address bus with address information. See
the GPSI section for more detail.
TXDAT
Transmit Data
TXDAT is an output, providing the serial bit stream for
transmission, including preamble, SFD data and FCS
field, if applicable.
Input/Output
Note that the TxDAT pin is multiplexed with the A31 pin.
TXEN
Transmit Enable
TXEN is an output, providing an enable signal for trans-
mission. Data on the TXDAT pin is not valid unless the
TXEN signal is HIGH.
Input/Output
Note that the TXEN pin is multiplexed with the A30 pin.
STDCLK
Serial Transmit Data Clock
STDCLK is an input, providing a clock signal for MAC
activity, both transmit and receive. Rising edges of the
STDCLK can be used to validate TXDAT output data.
Input
The STDCLK pin is multiplexed with the A29 pin.
Note that this signal must meet the frequency stability
requirement of the ISO 8802-3 (IEEE/ANSI 802.3)
specification for the crystal.
CLSN
Collision
CLSN is an input, indicating to the core logic that a
collision has occurred on the network.
Input/Output
Note that the CLSN pin is multiplexed with the A28 pin.
RXCRS
Receive Carrier Sense
RXCRS is an input. When this signal is HIGH, it indi-
cates to the core logic that the data on the RXDAT input
pin is valid.
Input/Output
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AM79C965AWW WAF | 制造商:Advanced Micro Devices 功能描述: |
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