參數(shù)資料
型號： S1C88848D0A0100
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁數(shù)： 88/174頁
文件大?。?/td> 1304K
代理商： S1C88848D0A0100
12
EPSON
S1C88848 TECHNICAL MANUAL
4 INITIAL RESET
____________
4.1.1 RESET terminal
Initial reset can be done by executed externally
___________
inputting a LOW level to the RESET terminal.
___________
Be sure to maintain the RESET terminal at LOW
level for the regulation time after the power on to
assure the initial reset.
___________
In addition, be sure to use the RESET terminal for
the first initial reset after the power is turned on.
___________
The RESET terminal is equipped with a pull-up
resistor. You can select whether or not to use by
mask option.
4.1.2 Simultaneous LOW level input at
input port terminals K00–K03
Another way of executing initial reset externally is to
input a LOW level simultaneously to the input ports
(K00–K03) selected by mask option.
Since there is a built-in time authorize circuit, be
sure to maintain the designated input port terminal
at LOW level for two seconds (when the oscillation
frequency fOSC1 = 32.768 kHz) or more to perform
the initial reset by means of this function.
However, the time authorize circuit is bypassed
during the SLEEP (standby) status and oscillation
stabilization waiting period, and initial reset is
executed immediately after the simultaneous LOW
level input to the designated input ports.
The combination of input ports (K00–K03) that can
be selected by mask option are as follows:
(1) Not use
(2) K00 & K01
(3) K00 & K01 & K02
(4) K00 & K01 & K02 & K03
For instance, if mask option (4) "K00 & K01 & K02
& K03" is selected, initial reset will take place when
the input level at input ports K00–K03 is simultane-
ously LOW.
When using this function, make sure that the
designated input ports do not simultaneously
switch to LOW level while the system is in normal
operation.
4.1.3 Initial reset sequence
After cancellation of the LOW level input to the
___________
RESET terminal, when the power is turned on, the
start-up of the CPU is held back until the oscillation
stabilization waiting time (128/fOSC1 sec.) has
elapsed. Figure 4.1.3.1 shows the operating
sequence following initial reset release.
Also, when using the initial reset by simultaneous
LOW level input into the input port, you should be
careful of the following points.
(1) During SLEEP status, since the time authoriza-
tion circuit is bypassed, an initial reset is
triggered immediately after a LOW level
simultaneous input value. In this case, the CPU
starts after waiting the oscillation stabilization
time, following cancellation of the LOW level
simultaneous input.
(2) Other than during SLEEP status, an initial reset
will be triggered 1–2 seconds after a LOW level
simultaneous input. In this case, since a reset
differential pulse (256/fOSC1 sec.) is generated
within the S1C88848, the CPU will start even if
the LOW level simultaneous input status is not
canceled.
PC
00-0000
Dummy
VECL
fOSC1
RESET
Internal initial reset
fOSC3
Internal address bus
Internal data bus
Internal read signal
128/fOSC1 [sec]
Oscillation stable waiting time
Dummy cycle
Reset exception processing
Fig. 4.1.3.1 Initial reset sequence
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