參數(shù)資料
型號： S1C88848D0A0100
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁數(shù)： 34/174頁
文件大?。?/td> 1304K
代理商： S1C88848D0A0100
S1C88848 TECHNICAL MANUAL
EPSON
121
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Remote Controller)
When set in this manner, if the corresponding
interrupt enable register is set to "1" and the
corresponding interrupt priority register is set to a
higher level than the setting of interrupt flags (I0
and I1), an interrupt will be generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag will be set to "1" by the occurrence of an
interrupt generation condition.
To accept the subsequent interrupt after interrupt
generation, re-setting of the interrupt flags (set
interrupt flag to lower level than the level indicated
by the interrupt priority registers, or execute the
RETE instruction) and interrupt factor flag reset are
necessary. The interrupt factor flag is reset to "0" by
writing "1".
At initial reset, FREM is reset to "0".
5.13.7 Programming notes
(1) The following programming steps are needed to
initialize the REM circuit (
τ clock, REM
interrupt circuit):
Write data at addresses 00FF28H and
00FF29H in that order within 80 machine
clocks (equivalent to ten 4-cycle instructions)
after release from initial reset.
With REMC = "0", the REM circuit must not
be stopped within cycle of 1
τ after data has
been written at address 00FF29H.
To initialize the REM interrupt circuit, write
"1" to the REM interrupt factor flag FREM to
clear it at least an interval of 2
τ after data has
been written at address 00FF29H.
(2) After initial reset, REMC is set to "1" to initialize
the carrier generation circuit. REMC can only be
reset to "0" after initialization (at least 32
machine cycles later).
(3) The REM circuit does not stop immediately
after REMC is reset to "0". It stops
synchronously with the interval
τ, during which
OSC3 must be held ON.
(4) With the REM circuit in operation, do not write
data at addresses 00FF29H and 00FF2AH (REM
interrupt generation counter and REM output
ON time setting register) during an interval of
one carrier before and after the rise of
τ.
(5) With the REM circuit in operation, do not write
data at addresses 00FF28H (
τ cycle setting
register).
(6) During the operation under hard-timer mode,
the REMSO register must be fixed at "0".
(7) If the RIC register is set again before a REM
interrupt occurs with the RIC register set, an
invalid interrupt may occur.
(8) The values that can be set in the REM interrupt
generation counter are from 0 to EH.
Remember, writing FH into RIC may cause an
error.
(9) Soft-timer mode cannot coexist with hard-timer
mode.
To use them in combination, stop the REM
circuit before selecting either.
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