參數(shù)資料
型號(hào)： S1C88848D0A0100
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁數(shù)： 159/174頁
文件大?。?/td> 1304K
代理商： S1C88848D0A0100
S1C88848 TECHNICAL MANUAL
EPSON
77
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Programmable Timer)
5.10.7 Interrupt function
The programmable timer can generate an interrupt
due to an underflow signal of each timer. Figure
5.10.7.1 shows the configuration of the
programmable timer interrupt circuit.
The respectively corresponding interrupt factor flag
FPTx is set to "1" and an interrupt is generated by
an underflow signal of timer x. Interrupt can also
be disabled by setting the interrupt enable register
EPTx corresponding to the interrupt factor flag.
In addition, a priority level of the programmable
timer interrupt for the CPU can be set at levels 0 to
3 using the interrupt priority registers PPT0 and
PPT1 (for timers 0 and 1), and PPT2 and PPT3 (for
timers 2 and 3).
For details on the above mentioned interrupt
control registers and the operation following
generation of an interrupt, see "5.15 Interrupt and
Standby Status".
The exception processing vector addresses of each
interrupt factor are respectively set as shown below.
Programmable timer 0 interrupt: 000008H
Programmable timer 1 interrupt: 000006H
Programmable timer 2 interrupt: 000028H
Programmable timer 3 interrupt: 000026H
When the 16-bit mode is selected, the interrupt
factor flag FPT0 (FPT2) is not set to "1" and a timer
0 (timer 2) interrupt cannot be generated. (In the 16-
bit mode, the interrupt factor flag FPT1 (FPT3) is set
to "1" by an underflow of the 16-bit counter.
EVIN0 input (K10)
Count data
PLPOL0
Prescaler
output clock
n
n-1
n-2
n-3
n-4
Input clock
to timer
PRUN0
FCSEL0
n-5
n-6
n-7
n-8
Fig. 5.10.6.1 Timing chart for pulse width measurement timer mode (timer 0)
Data
bus
Interrupt
request
Address
Timer 1 underflow
Interrupt factor
flag
FPT1
Address
Interrupt enable
register EPT1
Address
Timer 0 underflow
Interrupt factor
flag
FPT0
Address
Interrupt enable
register EPT0
Interrupt priority
level judgement
circuit
Address
Interrupt priority
register PPT0, PPT1
Interrupt
request
Address
Timer 3 underflow
Interrupt factor
flag
FPT3
Address
Interrupt enable
register EPT3
Address
Timer 2 underflow
Interrupt factor
flag
FPT2
Address
Interrupt enable
register EPT2
Interrupt priority
level judgement
circuit
Address
Interrupt priority
register PPT2, PPT3
Fig. 5.10.7.1 Configuration of programmable timer interrupt circuit
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