參數(shù)資料
型號(hào)： S1C88848D0A0100
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.2 MHz, MICROCONTROLLER, UUC192
封裝： DIE-192
文件頁(yè)數(shù)： 40/174頁(yè)
文件大?。?/td> 1304K
代理商： S1C88848D0A0100
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126
EPSON
S1C88848 TECHNICAL MANUAL
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Interrupt and Standby Status)
Interrupt factor flag that has been set to "1" is reset
to "0" by writing "1".
At initial reset, the interrupt factor flags are reset to "0".
Note: When executing the RETE instruction
without resetting the interrupt factor flag after
an interrupt has been generated, the same
interrupt will be generated. Consequently,
the interrupt factor flag corresponding to that
routine must be reset (writing "1") in the
interrupt processing routine.
5.15.3 Interrupt enable register
The interrupt enable register has a 1 to 1 corre-
spondence with each interrupt factor flag and
enable/disable of interrupt requests can be set.
When "1" is written to the interrupt enable register,
an interrupt request is enabled, and is disabled
when "0" is written. This register also permits
reading, thus making it possible to confirm that a
status has been set.
At initial reset, the interrupt enable registers are set
to "0" and shifts to the interrupt disable status.
Table 5.15.3.1 shows the correspondence between the
interrupt enable registers and the interrupt factor flags.
5.15.4 Interrupt priority register and
interrupt priority level
The interrupt priority registers shown in Table
5.15.4.1 are set to each system of interrupts and the
interrupt priority levels for the CPU can be set to
the optional priority level (0–3). As a result, it is
possible to have multiple interrupts that match the
system's interrupt processing priority levels.
The interrupt priority level between each system
can optionally be set to three levels by the interrupt
priority register. However, when more than one
system is set to the same priority level, they are
processed according to the default priority level.
Table 5.15.4.2 Setting of interrupt priority level
Table 5.15.3.1 Interrupt enable registers and interrupt factor flags
Table 5.15.4.1 Interrupt priority register
EPT1
EPT0
EPT3
EPT2
EK1
EK0H
EK0L
ESERR
ESREC
ESTRA
ESW100
ESW10
ESW1
ETM32
ETM8
ETM2
ETM1
EREM
Programmable timer 1
Programmable timer 0
Programmable timer 3
Programmable timer 2
K10–K11 input
K04–K07 input
K00–K03 input
Serial interface receiving error
Serial interface receiving completion
Serial interface transmitting completion
Stopwatch timer 100 Hz
Stopwatch timer 10 Hz
Stopwatch timer 1 Hz
Clock timer 32 Hz
Clock timer 8 Hz
Clock timer 2 Hz
Clock timer 1 Hz
Remote controller
Interrupt
Interrupt enable register
(00FF23 D7)
(00FF23 D6)
(00FF26 D7)
(00FF26 D6)
(00FF23 D5)
(00FF23 D4)
(00FF23 D3)
(00FF23 D2)
(00FF23 D1)
(00FF23 D0)
(00FF22 D6)
(00FF22 D5)
(00FF22 D4)
(00FF22 D3)
(00FF22 D2)
(00FF22 D1)
(00FF22 D0)
(00FF26 D5)
FPT1
FPT0
FPT3
FPT2
FK1
FK0H
FK0L
FSERR
FSREC
FSTRA
FSW100
FSW10
FSW1
FTM32
FTM8
FTM2
FTM1
FREM
Interrupt factor flag
(00FF25 D7)
(00FF25 D6)
(00FF27 D7)
(00FF27 D6)
(00FF25 D5)
(00FF25 D4)
(00FF25 D3)
(00FF25 D2)
(00FF25 D1)
(00FF25 D0)
(00FF24 D6)
(00FF24 D5)
(00FF24 D4)
(00FF24 D3)
(00FF24 D2)
(00FF24 D1)
(00FF24 D0)
(00FF27 D5)
Programmable timer 0–1 interrupt
Programmable timer 2–3 interrupt
K10–K11 input interrupt
K00–K07 input interrupt
Serial interface interrupt
Stopwatch timer interrupt
Clock timer interrupt
Remote controller interrupt
Interrupt
PPT0, PPT1
PPT2, PPT3
PK10, PK11
PK00, PK01
PSIF0, PSIF1
PSW0, PSW1
PTM0, PTM1
PREM0, PREM1
Interrupt priority register
(00FF21 D2, D3)
(00FF21 D4, D5)
(00FF21 D0, D1)
(00FF20 D6, D7)
(00FF20 D4, D5)
(00FF20 D2, D3)
(00FF20 D0, D1)
(00FF21 D6, D7)
P*1P*0
Interrupt priority level
1
0
1
0
1
0
Level 3
(IRQ3)
Level 2
(IRQ2)
Level 1
(IRQ1)
Level 0
(non)
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